MT48LC2M32B2P-6:G Micron Technology Inc, MT48LC2M32B2P-6:G Datasheet - Page 35
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MT48LC2M32B2P-6:G
Manufacturer Part Number
MT48LC2M32B2P-6:G
Description
IC, SDRAM, 64MBIT, 166MHZ, TSOP-86
Manufacturer
Micron Technology Inc
Type
SDRAMr
Series
-r
Specifications of MT48LC2M32B2P-6:G
Organization
2Mx32
Density
64Mb
Address Bus
13b
Access Time (max)
17/7.5/5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Memory Type
DRAM - Sychronous
Access Time
5.5ns
Page Size
64Mbit
Memory Case Style
TSOP
No. Of Pins
86
Operating Temperature Range
0°C To +70°C
Frequency
166MHz
Supply Voltage
3.3V
Format - Memory
RAM
Memory Size
64M (2Mx32)
Speed
167MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TFSOP (0.400", 10.16mm Width)
Filter Terminals
SMD
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48LC2M32B2P-6:G
Manufacturer:
MICRON
Quantity:
20 000
READ with Auto Precharge
WRITE with Auto Precharge
Figure 29:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. M 10/07 EN
READ With Auto Precharge Interrupted by a READ
Note:
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
Internal
States
rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ
to bank m is registered (Figure 29 on page 35).
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 30 on page 36).
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (Figure 31 on page 36).
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (Figure 32 on page 37).
DQM is LOW.
t
WR is met, where
COMMAND
ADDRESS
BANK m
BANK n
CLK
DQ
Page Active
T0
NOP
t
WR begins when the WRITE to bank m is registered. The last
READ - AP
BANK n,
Page Active
BANK n
COL a
T1
35
READ with Burst of 4
CAS Latency = 3 (BANK n)
T2
NOP
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WR is met, where
BANK m,
READ - AP
T3
BANK m
COL d
Interrupt Burst, Precharge
CAS Latency = 3 (BANK m)
READ with Burst of 4
TRANSITIONING DATA
T4
NOP
D
64Mb: x4, x8, x16 SDRAM
OUT
a
t
RP - BANK n
t
WR begins when the READ to
T5
NOP
D
a + 1
©2000 Micron Technology, Inc. All rights reserved.
OUT
T6
NOP
D
OUT
d
Commands
DON’T CARE
Idle
T7
NOP
t RP - BANK m
Precharge
D
d + 1
OUT