AD9912BCPZ Analog Devices Inc, AD9912BCPZ Datasheet - Page 8

• Manufacturer Part Number: AD9912BCPZ
• Manufacturer: Analog Devices Inc

Specifications of AD9912BCPZ

• Lead Free Status / RoHS Status: Compliant

AD9912
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2, 4, 6, 8
3, 5, 7
9, 10, 54, 55
11, 19, 23 to 26,
29, 30, 36, 42, 44,
45, 53
12, 13, 15, 16, 17,
18, 20, 21, 22
14, 46, 47, 49
27
28
31
Input/
Output
I
I
I
I/O
I
I
I
I
O
Pin Type
Power
Power
Power
3.3 V CMOS
Power
Power
Differential
input
Differential
input
DVDD_I/O
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
AVDD3
DVDD
DVDD
DVDD
AVDD
DVSS
DVSS
DVSS
DVSS
NC
NC
NC
NC
S1
S2
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Mnemonic
DVDD_I/O
DVSS
DVDD
S1, S2, S3, S4
AVDD
NC
AVDD3
SYSCLK
SYSCLKB
LOOP_FILTER
PIN 1
INDICATOR
Figure 2. Pin Configuration
(Not to Scale)
Rev. D | Page 8 of 40
AD9912
TOP VIEW
Description
I/O Digital Supply.
Digital Ground. Connect to ground.
Digital Supply.
Start-Up Configuration Pins. These pins are configured under program
control and do not have internal pull-up/pull-down resistors.
Analog Supply. Connect to a nominal 1.8 V supply.
No Connect. These unused pins can be left unconnected.
Analog Supply. Connect to a nominal 3.3 V supply.
System Clock Input. The system clock input has internal dc biasing and
should always be ac-coupled, except when using a crystal. Single-ended
1.8 V CMOS can also be used, but it may introduce a spur caused by an input
duty cycle that is not 50%. When using a crystal, tie the CLKMODESEL pin
to AVSS, and connect crystal directly to this pin and Pin 28.
Complementary System Clock. Complementary signal to the input
provided on Pin 27. Use a 0.01 μF capacitor to ground on this pin if the
signal provided on Pin 27 is single-ended.
System Clock Multiplier Loop Filter. When using the frequency multiplier to
drive the system clock, an external loop filter must be constructed and
attached to this pin. This pin should be pulled down to ground with 1 kΩ
resistor when the system clock PLL is bypassed. See Figure 46 for a diagram
of the system clock PLL loop filter.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DAC_RSET
AVDD3
AVDD3
AVDD
AVDD
AVSS
AVDD
FDBK_IN
FDBK_INB
AVSS
OUT_CMOS
AVDD3
AVDD
OUT
OUTB
AVSS