AD9912BCPZ Analog Devices Inc, AD9912BCPZ Datasheet - Page 34

• Manufacturer Part Number: AD9912BCPZ
• Manufacturer: Analog Devices Inc

Specifications of AD9912BCPZ

• Lead Free Status / RoHS Status: Compliant

AD9912
CMOS OUTPUT DIVIDER (S-DIVIDER) (REGISTER 0x0100 TO REGISTER 0x0106)
Register 0x0100 to Register 0x0103—Reserved
Register 0x0104—S-Divider
Table 21.
Bits
[7:0]
Register 0x0105—S-Divider (Continued)
Table 22.
Bits
[15:8]
Register 0x0106—S-Divider (Continued)
Table 23.
Bits
7
[6:1]
0
FREQUENCY TUNING WORD (REGISTER 0x01A0 TO REGISTER 0x01AD)
Register 0x01A0 to Register 0x01A5—Reserved
Register 0x01A6—FTW0 (Frequency Tuning Word)
Table 24.
Bits
[7:0]
Register 0x01A7—FTW0 (Frequency Tuning Word) (Continued)
Table 25.
Bits
[15:8]
Register 0x01A8—FTW0 (Frequency Tuning Word) (Continued)
Table 26.
Bits
[23:16]
Bit Name
S-divider
Bit Name
S-divider
Bit Name
Falling edge triggered
Reserved
S-divider/2
Bit Name
FTW0
Bit Name
FTW0
Bit Name
FTW0
Description
CMOS output divider. Divide ratio = 1 − 65,536. If the desired S-divider setting is greater than 65,536,
or if the signal on FDBK_IN is greater than 400 MHz, then Bit 0 in Register 0x0106 must be set. Note that
the actual S-divider is the value in this register plus 1; so to have an S-divider of 1, Register 0x0104 and
Register 0x0105 must both be 0x00. Register 0x0104 is the least significant byte.
Description
CMOS output divider. Divide ratio = 1 − 65,536. If the desired S-divider setting is greater than 65,536,
or if the signal on FDBK_IN is greater than 400 MHz, then Bit 0 in Register 0x0106 must be set. Note that
the actual S-divider is the value in this register plus 1; so to have an S-divider of 1, Register 0x0104 and
Register 0x0105 must both be 0x00. Register 0x104 is the least significant byte.
Description
Setting this bit inverts the reference clock before S-divider.
Reserved.
Setting this bit enables an additional /2 prescaler. See the CMOS Output Divider (S-Divider) section.
If the desired S-divider setting is greater than 65,536, or if the signal on FDBK_IN is greater than 400 MHz,
this bit must be set.
Description
These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio
of the AD9912 output frequency to its DAC system clock. Register 0x01A6 is the least significant byte
of the FTW. Note that the power-up default is defined by start-up Pin S1 to Pin S4. Updates to the FTW
results in an instantaneous frequency jump but no phase discontinuity.
Description
These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio
of the AD9912 output frequency to its DAC system clock. Register 0x01A6 is the least significant byte
of the FTW. Note that the power-up default is defined by start-up Pin S1 to Pin S4. Updates to the FTW
results in an instantaneous frequency jump but no phase discontinuity.
Description
These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio
of the AD9912 output frequency to its DAC system clock. Register 0x01A6 is the least significant byte
of the FTW. Note that the power-up default is defined by start-up Pin S1 to Pin S4. Updates to the FTW
results in an instantaneous frequency jump but no phase discontinuity.
Rev. D | Page 34 of 40