AD9912BCPZ Analog Devices Inc, AD9912BCPZ Datasheet - Page 5

• Manufacturer Part Number: AD9912BCPZ
• Manufacturer: Analog Devices Inc

Specifications of AD9912BCPZ

• Lead Free Status / RoHS Status: Compliant

AC SPECIFICATIONS
f
Table 2.
Parameter
FDBK_IN INPUT
SYSTEM CLOCK INPUT
CLOCK DRIVERS
S
= 1 GHz, DAC R
Input Frequency Range
Minimum Differential Input Level
SYSCLK PLL Bypassed
SYSCLK PLL Enabled
Crystal Resonator with SYSCLK PLL
HSTL Output Driver
HSTL Output Driver with 2× Multiplier
CMOS Output Driver
Input Frequency Range
Duty Cycle
Minimum Differential Input Level
VCO Frequency Range, Low Band
VCO Frequency Range, Auto Band
VCO Frequency Range, High Band
Maximum Input Rate of System
Without SYSCLK PLL Doubler
With SYSCLK PLL Doubler
Enabled
Crystal Resonator Frequency Range
Maximum Crystal Motional Resistance
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
Jitter (12 kHz to 20 MHz)
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
Subharmonic Spur Level
Jitter (12 kHz to 20 MHz)
(AVDD3/Pin 37) @ 3.3 V
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
Clock PFD
Input Frequency Range
Multiplication Range
Minimum Differential Input Level
Input Frequency Range
Multiplication Range
Input Duty Cycle
Minimum Differential Input Level
SET
= 10 kΩ, unless otherwise noted. Power supply pins within the range specified in the DC Specifications section.
Min
10
225
40
250
45
632
700
810
900
11
4
632
6
8
632
10
20
48
400
45
0.008
45
Typ
50
115
1.5
115
−35
1.6
55
3
Rev. D | Page 5 of 40
Max
400
1000
55
810
900
1000
100
200
66
100
132
50
100
725
52
165
725
55
165
150
65
4.6
Unit
MHz
mV p-p
V/μs
MHz
%
mV p-p
MHz
MHz
MHz
MHz
MHz
mV p-p
MHz
%
mV p-p
MHz
Ω
MHz
%
ps
ps
MHz
%
ps
dBc
ps
MHz
%
ns
Test Conditions/Comments
Pin 40, Pin 41
−12 dBm into 50 Ω; must be ac-coupled
Pin 27, Pin 28
Maximum f
Equivalent to 316 mV swing on each leg
When in the range, use the low VCO band exclusively
When in the range, use the VCO auto band select
When in the range, use the high VCO band exclusively
Integer multiples of 2, maximum PFD rate and system clock
frequency must be met
Equivalent to 316 mV swing on each leg
Integer multiples of 8
Deviating from 50% duty cycle may adversely affect
spurious performance
Equivalent to 316 mV swing on each leg
AT cut, fundamental mode resonator
See the SYSCLK Inputs section for recommendations
See Figure 27 for maximum toggle rate
100 Ω termination across OUT/OUTB, 2 pF load
f
through Figure 14 for test conditions)
100 Ω termination across OUT/OUTB, 2 pF load
Without correction
f
for test conditions)
See Figure 29 for maximum toggle rate; the S-divider
should be used for low frequencies because the FDBK_IN
minimum frequency is 10 MHz
With 20 pF load and up to 150 MHz
With 20 pF load
OUT
OUT
= 155.52 MHz, 50 MHz system clock input (see Figure
= 622.08 MHz, 50 MHz system clock input (see Figure
OUT
is 0.4 × f
SYSCLK
AD9912
12
15