AD9912BCPZ Analog Devices Inc, AD9912BCPZ Datasheet - Page 30

• Manufacturer Part Number: AD9912BCPZ
• Manufacturer: Analog Devices Inc

Specifications of AD9912BCPZ

• Lead Free Status / RoHS Status: Compliant

AD9912
I/O REGISTER MAP
All address and bit locations that are left blank in Table 12 are unused.
Table 12.
Addr
(Hex)
Serial port configuration and part identification
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
Power-down and reset
0x0010
0x0011
0x0012
0x0013
System clock
0x0020
0x0021
0x0022
CMOS output divider (S-divider)
0x0100
0x0101
to
0x0103
0x0104
and
0x0105
0x0106
Frequency tuning word
0x01A0
to
0x01A5
0x01A6
0x01A7
0x01A8
0x01A9
0x01AA
0x01AB
0x01AC
0x01AD
Doubler and output drivers
0x0200
0x0201
Type
RO
RO
AC
M, AC
M
M
M
M
M
M
M
M
M
1
Name
Serial
config.
Reserved
Part ID
Serial
options
Power-
down and
enable
Reserved
Reset
N-divider
Reserved
PLL
parameters
Reserved
Reserved
S-divider
Reserved
FTW0
(frequency
tuning
word)
Phase
HSTL driver
CMOS driver
Bit 7
SDO
active
PD HSTL
driver
PD fund
DDS
VCO auto
range
Falling
edge
triggered
Bit 6
LSB first
(buffered)
Enable
CMOS
driver
Bit 5
Soft
reset
Enable
output
doubler
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Bit 4
Long
instruction
PD
SYSCLK
PLL
OPOL
(polarity)
DDS phase word, Bits[7:0]
LSB: Register 0x0104
LSB: Register 0x01A6
S-divider, Bits[15:0]
FTW0, Bits[47:0]
Part ID
Long
instruction
Bit 3
S-div/2
reset
2× refer-
ence
DDS phase word, Bits[13:8]
N-divider, Bits[4:0]
Bit 2
Soft reset
VCO range
Bit 1
LSB first
(buffered)
Full PD
S-divider
reset
Charge pump current,
HSTL output doubler,
Bits[1:0]
Bits[1:0]
S-divider/2
Bit 0
SDO
active
Read buffer
register
Register
update
Digital PD
DDS reset
CMOS mux
Default
(Hex)
0x18
0x00
0x02
0x09
0x00
0x00
0xC0 or
0xD0
0x00
0x00
0x00
0x12
0x00
0x04
0x30
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x00
Start-up
cond.
Start-up
cond.
0x00
0x00
0x05
0x00