TMC22152KHC Fairchild Semiconductor, TMC22152KHC Datasheet - Page 8

• Manufacturer Part Number: TMC22152KHC
• Manufacturer: Fairchild Semiconductor

Specifications of TMC22152KHC

• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

TMC22x5y
Control Register Map
The TMC22x5y is initialized and controlled by a set of regis-
ters which determine the operating modes.
An external controller is employed to write and read the
Control Registers through either the 8-bit parallel or 2-line
serial interface port. The parallel port, D
pins CS, R/W, and A
and SCL.
8
Reg
00
00
00
00
00
01
01
01
01
01
01
01
01
02
02
02
02
02
02
02
03
03
03
03
03
04
05
5-3
1-0
5-4
7-5
3-2
7-0
7-0
Bit
7
6
2
7
6
5
4
3
2
1
0
7
6
3
2
1
0
4
1
0
Chroma Processor Control
Name
SRST
HRST
SET
DHVEN
STD
IPMUX
IP8B
TDEN
TBLK
IPCMSB
ABMUX
CKSEL
VIPEN
LOCK
BLM
KILD
DMODBY
CINT
BLFS
CCEN
CCOR
GAUBY
GAUSEL
BTH
PED
Input Processor Control
Burst Loop Control
1-0
Burst Threshold
Global Control
. The serial port is controlled by SDA
Pedestal
Software reset
Hardware reset
SET pin function
Output H&V sync enable
Selects video standard
reserved, set to zero
Input mux control
8 bit input format
TRS detect enable
TRS blank enable
Chroma input msb invert
AB mux control
Input clock rate select
reserved, set to zero
Video Input Processor
enable
Global lock mode
BLL lock mode
Color kill disable
Demod bypass
C
Burst loop filter select
Chroma coring enable
Chroma coring threshold
Gaussian filter bypass
Gaussian filter select
Burst threshold
Pedestal level
B
C
R
interpolation enable
Function
7-0
, is governed by
Reg
0A
0A
0A
0A
0A
0A
0B
0B
0B
0B
0B
0B
0C
0C
0C
06
06
06
06
06
06
07
07
07
07
07
07
07
07
08
08
09
09
7-6
3-2
7-2
1-0
7-4
3-0
6-5
4-3
4-2
7-6
Bit
5
4
1
0
7
6
5
4
3
2
1
0
7
2
1
0
7
6
5
1
0
5
4
Name
ANEN
ANR
ANT
ANSEL
NOTCH
LS1BY
LS1IN
LS2DLY
SPLIT
BSFBY
BSFSEL
BSFMSB
GRSDLY
MIDS
CLMP
PCKF
VSTD
OP8B
OPLMT
MSEN
OPCMSB
YBAL
BUREN
FMT422
CDEC
YUVT
DRSEN
DRSCK
ADAPT
YCES
YCSEL
Comb Processor Control
Luma Processor Control
Comb Filter Control
Mid-Sync Level
Output Control
Extended DRS
reserved, set to zero
Adaptive notch enable
Adaptive notch rounding
Adaptive notch threshold
Adaptive notch select
Notch enable
Line store 1 bypass
Line store 1 input
Line store 2 delay
Line store 2 data width
Bandsplit filter bypass
Bandsplit filter select
Inverts msb of bandsplit
filter
Delays input to GRS
decode by 1H
Mid-sync level
Black level clamp selection
Clock rate
Video standard
Output rounded to 8 bits
Output limit select
Mixed sync enable
Chroma output msb invert
Luma color correction
Output burst enable
Enables C
C
Enables D1 output
reserved, set to zero
DRS output enable
DRS data rate
Adaption mode
YC input error signal
control
luma/chroma comb filter
select
B
C
PRODUCT SPECIFICATION
R
decimation enable
Function
B
C
R
output mux