TMC22053KHC Fairchild Semiconductor, TMC22053KHC Datasheet - Page 57

• Manufacturer Part Number: TMC22053KHC
• Manufacturer: Fairchild Semiconductor

Specifications of TMC22053KHC

• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

PRODUCT SPECIFICATION
Simple Luma Color Correction
If the YBAL register bit is set HIGH, and the luma data
reaches or exceeds the luma limits, there should be no C
or UV data at that time; therefore the color data are set to
ZERO. If YBAL is set LOW then the C
unaffected by the luma data.
C
The msb of the C
MSBO register bit HIGH. As this would affect the chroma
blanking level, this circuit appears at the output of the
MATRIX circuit.
Output Rounding
For compatibility with 8 bit systems, the output of the matrix
can be rounded to 8 bits by setting the RND8 register bit
HIGH.
Output Formats
RGB Outputs
The RGB data are simply passed through to the decoder out-
put. When the DRSEN register bit is HIGH the DRS data are
inserted into the green data path only.
YUV Outputs
The YUV data are simply passed through to the decoder out-
put. When the DRSEN register bit is HIGH the DRS data are
inserted into the luminance data path only.
YC
The YC
the CDEC, F422, and YUVT register bits. These output
modes are summarized in .
When CDEC is HIGH and F422 is HIGH, the G/Y output is
set to 64 and the B/U output is set to 512 between the EAV
TRS data word and the first preamble word of the SAV TRS,
i.e. during the digital horizontal blanking period. When
YUVT is HIGH, R/V is set to 512, 64, 512, 64, etc., starting
after the EAV TRS data word and finishing before the SAV
preamble.
Table 14. Output Format
B
B
C
CDEC
C
R
R
0
1
1
1
B
Outputs
MSB Inversion
C
R
data can be output in 3 ways, depending upon
YUVT
B
C
0
0
1
x
R
data can be inverted by setting the
F422
x
0
1
x
B
C
G or Y
R
G/Y
/UV data are
Y
Y
Y
B
B or C
C
C
C
R
B/U
C
B
B
C
C
B
R
R
B
Decimating C
Whenever the CDEC register bit is set HIGH the B/U and
R/V data are simply sample dropped, with respect to
CBSEL, to produce the multiplexed C
PCK clock rate. If the input was initially D1 then the
dropped samples will be the interpolated samples produced
by the chroma interpolation filter. If however the C
are simply weighted UV data then the sample dropped
demodulated color difference signals (UV) will alias around
0.25 of the normalized sample frequency.
Multiplexed YC
Inserted)
When both the CDEC and YUVT register bits are HIGH the
Y, C
27MHz (PXCK) data stream with embedded TRS words.
The TRS words are generated based on the HSYNC or
VSYNC pulses provided to the decoder, and the internally
derived horizontal blanking (HBLK), vertical blanking
(VBLK), and the field flag (FLD). This mode of operation is
only available if a line locked PXCK clock, at 27MHz, is
provided. The TRS words will be generated with respect to
the HSYNC\ signal as per the ANSI/SMPTE 125M-1992
and CCIR 656 specifications.
YC Outputs
The YC data are passed through to the decoder output. When
the DRSEN register bit is HIGH the DRS data are inserted
into the luminance data path only. The luminance appears on
G/Y, chrominance is on B/U and the R/V output is set to
zero, by setting the V_scalar to zero.
The LDV Clock
The decoder can accept clocks at either the pixel clock rate
(PCK) or at twice the pixel clock rate (PXCK). In the cases
where the clock provided is PXCK, for example the genlock
mode, the output data still needs to be at the PCK clock rate.
To aid in the design of external circuitry a LDV clock is pro-
vided if the LDVIO register bit is LOW, if LDVIO is HIGH
then the LDV pin becomes an input for an external clock.
If an external LDV clock is employed the user must ensure
that the rising edge of the external LDV meets the specified
setup and hold times relative to the input CLOCK pin. The
selection of which clock to use on the decoder output is set
by the OPSEL register bit. When OPSEL is set LOW the
output is clocked at the same rate as the clock on the
CLOCK pin, and when OPSEL is set HIGH the output is
clocked by the internal or external clock on the LDV pin.
B
, and C
R or C
D1 data
R/V
C
0
R
R
component data are multiplexed into a single
R
B
C
B
C
R
[4:4:4] data
[4:2:2] data
[4:2:2] data
[4:2:2] data & D1 output
R
Data
Output (TRS Words
Comments
B
C
R
data stream at the
B
TMC22x5y
C
R
data
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