STM8AF6246TDSSSX STMicroelectronics, STM8AF6246TDSSSX Datasheet - Page 35
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STM8AF6246TDSSSX
Manufacturer Part Number
STM8AF6246TDSSSX
Description
8 BITS MICROCONTR
Manufacturer
STMicroelectronics
Series
STM8Ar
Datasheet
1.STM8AF5289TCY.pdf
(106 pages)
Specifications of STM8AF6246TDSSSX
Core Processor
STM8A
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
32-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM8AF6246TDSSSX
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STM8AF6246TDSSSX
Manufacturer:
ST
Quantity:
20 000
STM8AF52/62xx, STM8AF51/61xx
Table 12.
1. In Halt/Active-halt mode, this pin behaves as follows:
2. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, week pull-up and protection diode to V
3. The PD1 pin is in input pull-up during the reset phase and after reset release.
4. If this pin is configured as interrupt pin, it will trigger the TLI.
66 52
67 53 37
68 54 38
69 55 39
70 56 40
71
72
73 57 41 25 PD0/TIM3_CH2 I/O
74 58 42 26
75 59 43 27 PD2/TIM3_CH1 I/O
76 60 44 28 PD3/TIM2_CH2 I/O
77 61 45 29
78 62 46 30
79 63 47 31
80 64 48 32
Pin number
- The input/output path is disabled.
- If the HSE clock is used for wakeup, the internal weak pull-up is disabled.
- If the HSE clock is off, the internal weak pull-up setting is used. It is configured through Px_CR1[7:0] bits of the
corresponding port control register. Px_CR1[7:0] bits must be set correctly to ensure that the pin is not left floating in
Halt/Active-halt mode.
not implemented)
-
-
-
-
-
STM8A microcontroller family pin description (continued)
-
-
-
-
-
-
-
PE3/TIM1_BKIN I/O
PD4/TIM2_CH1/
PE0/CLK_CCO I/O
PE2/I
PE1/I
LINUART_RX
LINUART_TX
PD1/SWIM
PD7/TLI
Pin name
BEEP
PD5/
PD6/
PE4
PI6
PI7
2
2
C_SDA
C_SCL
(4)
(3)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Input
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
Doc ID 14395 Rev 8
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
HS O3
HS O4
HS O3
HS O3
HS O3
— O1
— O1
— O1 T
— O1 T
— O3
— O1
— O1
— O1
— O1
— O1
Output
X
X
X
X
X
X
X
X
X
X
X
X
X
(2)
(2)
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
function
Port D0
Port D1
Port D2
Port D3
Port D4
Port D5
Port D6
Port D7
Port E4
Port E3
Port E2
Port E1
Port E0
Port I6
Port I7
reset)
(after
Main
Pinouts and pin description
data transmit
Configurable
clock output
data receive
break input
SWIM data
channel 2
channel 1
channel 2
channel 1
alternate
LINUART
LINUART
function
Timer 1 -
I
Timer 3 -
Timer 3 -
Timer 2 -
Timer 2 -
interface
Top level
I
interrupt
Default
2
2
C clock
C data
—
—
—
BEEP output
after remap
[option bit]
TIM1_BKIN
TIM2_CH3
CLK_CCO
ADC_ETR
Alternate
function
[AFR3]/
DD
[AFR2]
[AFR1]
[AFR0]
[AFR7]
—
—
—
—
—
—
—
—
—
—
—
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