STM8AF6246TDSSSX STMicroelectronics, STM8AF6246TDSSSX Datasheet - Page 105
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STM8AF6246TDSSSX
Manufacturer Part Number
STM8AF6246TDSSSX
Description
8 BITS MICROCONTR
Manufacturer
STMicroelectronics
Series
STM8Ar
Datasheet
1.STM8AF5289TCY.pdf
(106 pages)
Specifications of STM8AF6246TDSSSX
Core Processor
STM8A
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
32-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM8AF6246TDSSSX
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STM8AF6246TDSSSX
Manufacturer:
ST
Quantity:
20 000
STM8AF52/62xx, STM8AF51/61xx
Table 55.
3&-Jan-2011
Date
Document revision history (continued)
(continued)
Revision
Rev 8
Renamed Fast Active Halt mode to Active-halt mode with regulator
on, and Slow Active Halt mode to Active-halt mode with regulator off,
updated
Total current consumption in Halt and Active-halt modes. General
conditions for V
stated. I
renamed t
Removed note 1 in
1 below
Removed note 3 in
and Slow mode. General conditions for V
150
Removed note 2 in
Table 36: Flash program memory/data EEPROM
Removed note 1 in
value in
memory.
Added t
characteristics.
Added recommendation concerning NRST pin level, and power
consumption sensitive applications, above
Recommended reset pin
value.
Update
specifications.
Updated
Moved know limitations to separate errata sheet.
Added “not recommended for new design” note to device family 51,
memory size 7 and 9, and temperature range B, in
Ordering information
Added Raisonance compiler in
Doc ID 14395 Rev 8
°C.
IFP(NRST)
DD(FAH)
Note 1
Figure 10: f
Table 37: Flash program memory
Section 5.6: Low-power operating
Note 1
WU(AH)
in
DD
and I
in
.
and renamed V
Table 41: TIM 1, 2, 3, and 4 electrical
Table 42: SPI
applied. T
Table 25: General operating
Table 27: Total current consumption in Run, Wait
Table 32: HSE external clock characteristics
Table 38: Data
CPUmax
DD(SAH)
scheme.
protection, and updated external capacitor
versus V
renamed I
A
Changes
= -40 °C to 55 °C unless otherwise
Section 13.2: Software
F(NRST)
characteristics.
memory. Modified T
DD
DD(AH);
.
t
IFP
and
DD
Figure 38:
modes, and
in
apply, T
t
Table 38: Data
Table 40: NRST pin
WU(FAH)
conditions, and note
memory.
Revision history
Figure 48:
A
WE
= -40 °C to
tools.
and t
Table 28:
maximum
WU(SAH)
105/106
and