PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 196

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 20-2:
DS61168D-page 196
Legend:
R = Readable bit
-n = Value at POR
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 14
bit 13
bit 12
bit 11-8
Note 1:
Range
31:24
23:16
15:8
7:0
Bit
2:
3:
4:
ALRMEN: Alarm Enable bit
1 = Alarm is enabled
0 = Alarm is disabled
CHIME: Chime Enable bit
1 = Chime is enabled – ARPT<7:0> is allowed to rollover from 0x00 to 0xFF
0 = Chime is disabled – ARPT<7:0> stops once it reaches 0x00
PIV: Alarm Pulse Initial Value bit
When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.
When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.
ALRMSYNC: Alarm Sync bit
1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read.
0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTC
AMASK<3:0>: Alarm Mask Configuration bits
0000 = Every half-second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29, once every four years)
1010 = Reserved; do not use
1011 = Reserved; do not use
11xx = Reserved; do not use
ALRMEN
This register is reset only on a Power-on Reset (POR).
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME = 0.
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
This assumes a CPU read will execute in less than 32 PBCLKs.
31/23/15/7
R/W-0
R/W-0
The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple
bits may be changing, which are then synchronized to the PB clock domain
clocks away from a half-second rollover
Bit
U-0
U-0
—
—
(2,3)
RTCALRM: RTC ALARM CONTROL REGISTER
30/22/14/6
CHIME
R/W-0
R/W-0
Bit
U-0
U-0
—
—
(3)
(3)
(2,3)
W = Writable bit
‘1’ = Bit is set
29/21/13/5
(4)
PIV
R/W-0
R/W-0
(3)
Bit
U-0
U-0
—
—
(3)
Preliminary
ALRMSYNC
28/20/12/4
(3)
ARPT<7:0>
R/W-0
Bit
U-0
U-0
R-0
—
—
(4)
27/19/11/3
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(3)
R/W-0
R/W-0
Bit
U-0
U-0
—
—
(1)
26/18/10/2
© 2011-2012 Microchip Technology Inc.
R/W-0
R/W-0
Bit
AMASK<3:0>
U-0
U-0
—
—
x = Bit is unknown
25/17/9/1
R/W-0
R/W-0
Bit
U-0
U-0
—
—
(3)
24/16/8/0
R/W-0
R/W-0
Bit
U-0
U-0
—
—