PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 167

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

REGISTER 16-1:
© 2011-2012 Microchip Technology Inc.
bit 16
bit 15
bit 14
bit 13
bit 12
bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
Note 1:
2:
3:
ENHBUF: Enhanced Buffer Enable bit
1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled
ON: SPI Peripheral On bit
1 = SPI Peripheral is enabled
0 = SPI Peripheral is disabled
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters in Idle mode
0 = Continue operation in Idle mode
DISSDO: Disable SDOx pin bit
1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register
0 = SDOx pin is controlled by the module
When AUDEN = 1:
MODE32
When AUDEN = 0:
MODE32
SMP: SPI Data Input Sample Phase bit
Master mode (MSTEN = 1):
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode (MSTEN = 0):
SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.
CKE: SPI Clock Edge Select bit
1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
SSEN: Slave Select Enable (Slave mode) bit
1 = SSx pin used for Slave mode
0 = SSx pin not used for Slave mode, pin controlled by port function.
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
DISSDI: Disable SDI bit
1 = SDI pin is not used by the SPI module (pin is controlled by PORT function)
0 = SDI pin is controlled by the SPI module
When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit can only be written when the ON bit = 0.
This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).
1
1
0
0
1
0
0
SPIxCON: SPI CONTROL REGISTER (CONTINUED)
MODE16
MODE16
1
0
1
0
x
1
0
(1)
24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame
16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame
32-bit
16-bit
8-bit
Communication
Communication
(3)
(2)
Preliminary
PIC32MX1XX/2XX
DS61168D-page 167