PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 111

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

REGISTER 9-7:
© 2011-2012 Microchip Technology Inc.
Legend:
R = Readable bit
-n = Value at POR
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 14-9
bit 8
bit 7
bit 6
bit
bit 4
bit 3
bit 2
bit 1-0
Note 1:
Range
31:24
23:16
15:8
Bit
7:0
2:
CHBUSY: Channel Busy bit
1 = Channel is active or has been enabled
0 = Channel is inactive or has been disabled
Unimplemented: Read as ‘0’
CHCHNS: Chain Channel Selection bit
1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
CHEN: Channel Enable bit
1 = Channel is enabled
0 = Channel is disabled
CHAED: Channel Allow Events If Disabled bit
1 = Channel start/abort events will be registered, even if the channel is disabled
0 = Channel start/abort events will be ignored if the channel is disabled
CHCHN: Channel Chain Enable bit
1 = Allow channel to be chained
0 = Do not allow channel to be chained
CHAEN: Channel Automatic Enable bit
1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete
0 = Channel is disabled on block transfer complete
Unimplemented: Read as ‘0’
CHEDET: Channel Event Detected bit
1 = An event has been detected
0 = No events have been detected
CHPRI<1:0>: Channel Priority bits
11 = Channel has priority 3 (highest)
10 = Channel has priority 2
01 = Channel has priority 1
00 = Channel has priority 0
The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).
When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.
31/23/15/7
CHBUSY
CHEN
R/W-0
R/W-0
Bit
U-0
U-0
—
—
(2)
DCHxCON: DMA CHANNEL x CONTROL REGISTER
30/22/14/6
CHAED
R/W-0
Bit
U-0
U-0
U-0
—
—
—
(2)
W = Writable bit
‘1’ = Bit is set
29/21/13/5
CHCHN
R/W-0
Bit
U-0
U-0
U-0
—
—
—
(1)
Preliminary
28/20/12/4
CHAEN
R/W-0
Bit
U-0
U-0
U-0
—
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
Bit
U-0
U-0
U-0
U-0
—
—
—
—
PIC32MX1XX/2XX
26/18/10/2
CHEDET
Bit
U-0
U-0
U-0
R-0
—
—
—
x = Bit is unknown
25/17/9/1
R/W-0
Bit
U-0
U-0
U-0
—
—
—
CHPRI<1:0>
DS61168D-page 111
CHCHNS
24/16/8/0
R/W-0
R/W-0
Bit
U-0
U-0
—
—
(1)