PIC18LF13K22-E/ML Microchip Technology, PIC18LF13K22-E/ML Datasheet - Page 84
![8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 QFN 4x4mm TUBE](/photos/16/12/161232/qfn-20-bottom_sml.jpg)
PIC18LF13K22-E/ML
Manufacturer Part Number
PIC18LF13K22-E/ML
Description
8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 QFN 4x4mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF13K22-ISS.pdf
(388 pages)
2.PIC18LF13K22-ISS.pdf
(12 pages)
3.PIC18LF13K22-ISS.pdf
(36 pages)
Specifications of PIC18LF13K22-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
A/d Bit Size
10 bit
A/d Channels Available
12
Height
0.88 mm
Length
4 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.8 V, 2.7 V
Width
4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 84 of 388
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PIC18F1XK22/LF1XK22
TABLE 8-2:
DS41365D-page 84
ANSEL
INTCON
INTCON2
IOCA
LATA
PORTA
SLRCON
TRISA
WPUA
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1:
Name
2:
RA<5:4> and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
GIE/GIEH PEIE/GIEL
RABPU
ANS7
Bit 7
—
—
—
—
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
INTEDG0 INTEDG1 INTEDG2
ANS6
Bit 6
—
—
—
—
—
—
TRISA5
LATA5
TMR0IE
WPUA5
IOCA5
RA5
ANS5
Bit 5
—
(1)
(1)
(1)
TRISA4
LATA4
WPUA4
INT0IE
Preliminary
IOCA4
RA4
ANS4
Bit 4
—
(1)
(1)
(1)
WPUA3
IOCA3
RABIE
RA3
ANS3
Bit 3
—
—
—
—
(2)
(2)
(2)
TMR0IP
TMR0IF
WPUA2
TRISA2
IOCA2
LATA2
ANS2
SLRC
Bit 2
RA2
TRISA1
WPUA1
INT0IF
IOCA1
LATA1
ANS1
SLRB
Bit 1
RA1
2010 Microchip Technology Inc.
—
TRISA0
WPUA0
RABIF
RABIP
IOCA0
LATA0
ANS0
SLRA
Bit 0
RA0
Values on
Reset
page
260
257
257
260
260
260
260
260
257
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