PIC18LF13K22-E/ML Microchip Technology, PIC18LF13K22-E/ML Datasheet - Page 222
![8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 QFN 4x4mm TUBE](/photos/16/12/161232/qfn-20-bottom_sml.jpg)
PIC18LF13K22-E/ML
Manufacturer Part Number
PIC18LF13K22-E/ML
Description
8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 QFN 4x4mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF13K22-ISS.pdf
(388 pages)
2.PIC18LF13K22-ISS.pdf
(12 pages)
3.PIC18LF13K22-ISS.pdf
(36 pages)
Specifications of PIC18LF13K22-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
A/d Bit Size
10 bit
A/d Channels Available
12
Height
0.88 mm
Length
4 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.8 V, 2.7 V
Width
4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F1XK22/LF1XK22
DS41365D-page 222
FIGURE 17-2:
V
C1RSEL
FVR
REF
C12IN0-
C12IN1-
C12IN2-
C12IN3-
C1IN+
C1CH<1:0>
0
1
MUX
C1V
C1R
COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
REF
0
1
2
3
0
1
2
MUX
MUX
Note 1:
2:
3:
4:
C1V
C1V
C1SP
When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
Q1 and Q3 are phases of the four-phase system clock (F
Q1 is held high during Sleep mode.
Positive going pulse generated on both falling and rising edges of the bit.
IN
IN
-
+
+
-
From TMR1L[0]
C1
C1ON
C1POL
(1)
Preliminary
Q3*RD_CM1CON0
(4)
Q1
D
NReset
Q
D
EN
C1OUT
C1SYNC
Q
D
EN
0
1
CL
Q
2010 Microchip Technology Inc.
RD_CM1CON0
OSC
To PWM Logic
).
SYNCC1OUT
Data Bus
Set C1IF
C1OE
To
C1OUT
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