PIC18LF13K22-E/ML Microchip Technology, PIC18LF13K22-E/ML Datasheet - Page 26
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PIC18LF13K22-E/ML
Manufacturer Part Number
PIC18LF13K22-E/ML
Description
8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 QFN 4x4mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF13K22-ISS.pdf
(388 pages)
2.PIC18LF13K22-ISS.pdf
(12 pages)
3.PIC18LF13K22-ISS.pdf
(36 pages)
Specifications of PIC18LF13K22-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
A/d Bit Size
10 bit
A/d Channels Available
12
Height
0.88 mm
Length
4 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.8 V, 2.7 V
Width
4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F1XK22/LF1XK22
FIGURE 2-7:
TABLE 2-5:
DS41365D-page 26
CONFIG1H
INTCON
OSCCON
OSCCON2
OSCTUNE
IPR2
PIE2
PIR2
T1CON
Legend:
Note 1:
Clock Monitor Output
Name
Sample Clock
Note:
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
OSCFIF
System
GIE/GIEH
Output
INTSRC
OSCFIP
OSCFIE
OSCFIF
Clock
IDLEN
RD16
IESO
Bit 7
(Q)
—
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
FSCM TIMING DIAGRAM
PEIE/GIEL
FCMEN
T1RUN
PLLEN
IRCF2
Bit 6
C1IP
C1IE
C1IF
—
T1CKPS1
PCLKEN
TMR0IE
IRCF1
Test
TUN5
C2IP
C2IE
Bit 5
C2IF
—
Preliminary
T1CKPS0
PLL_EN
INT0IE
IRCF0
TUN4
Bit 4
EEIP
EEIE
EEIF
—
T1OSCEN
FOSC3
RABIE
BCLIP
BCLIE
BCLIF
OSTS
TUN3
Bit 3
—
Test
Oscillator
Failure
T1SYNC
TMR0IF
HFIOFS
PRI_SD
FOSC2
TUN2
Bit 2
—
—
—
TMR1CS
TMR3IP
TMR3IE
TMR3IF
HFIOFL
FOSC1
INT0IF
SCS1
TUN1
Bit 1
2010 Microchip Technology Inc.
Detected
Failure
TMR1ON
LFIOFS
FOSC0
RABIF
SCS0
TUN0
Bit 0
Test
—
—
—
Values on
Reset
page
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