PIC18F96J65-I/PF Microchip Technology, PIC18F96J65-I/PF Datasheet - Page 468
![96KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm TRAY](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC18F96J65-I/PF
Manufacturer Part Number
PIC18F96J65-I/PF
Description
96KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(8 pages)
3.PIC18F66J65-IPT.pdf
(480 pages)
4.PIC18F66J65-IPT.pdf
(4 pages)
5.PIC18F66J65-IPT.pdf
(10 pages)
6.PIC18F96J60-IPT.pdf
(24 pages)
Specifications of PIC18F96J65-I/PF
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
96KB (48K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F96J65-I/PF
Manufacturer:
Microchip
Quantity:
251
Company:
Part Number:
PIC18F96J65-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F66J65-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- PIC18F66J65-IPT PDF datasheet #5
- PIC18F96J60-IPT PDF datasheet #6
- Current page: 468 of 480
- Download datasheet (8Mb)
PIC18F97J60 FAMILY
Extended Instruction Set
External Clock Input (EC Modes) ....................................... 44
External Memory Bus ....................................................... 109
F
Fail-Safe Clock Monitor ............................................ 349, 360
Fast Register Stack ............................................................ 77
Firmware Instructions ....................................................... 363
Flash Configuration Words ......................................... 72, 349
Flash Program Memory ...................................................... 99
FSCM. See Fail-Safe Clock Monitor.
DS39762E-page 468
Synchronous Slave Mode ........................................ 326
ADDFSR .................................................................. 406
ADDULNK ................................................................ 406
CALLW ..................................................................... 407
MOVSF .................................................................... 407
MOVSS .................................................................... 408
PUSHL ..................................................................... 408
SUBFSR .................................................................. 409
SUBULNK ................................................................ 409
16-Bit Byte Select Mode .......................................... 115
16-Bit Byte Write Mode ............................................ 113
16-Bit Data Width Modes ......................................... 112
16-Bit Mode Timing .................................................. 116
16-Bit Word Write Mode ........................................... 114
21-Bit Addressing ..................................................... 111
8-Bit Data Width Mode ............................................. 117
8-Bit Mode Timing .................................................... 118
Address and Data Line Usage (table) ...................... 111
Address and Data Width .......................................... 111
Address Shifting ....................................................... 111
Control ..................................................................... 110
I/O Port Functions .................................................... 109
Operation in Power-Managed Modes ...................... 119
Program Memory Modes ......................................... 112
Wait States ............................................................... 112
Weak Pull-ups on Port Pins ..................................... 112
and the Watchdog Timer .......................................... 360
Exiting Operation ..................................................... 360
Interrupts in Power-Managed Modes ....................... 361
POR or Wake-up From Sleep .................................. 361
Associated Registers ............................................... 107
Control Registers ..................................................... 100
Erase Sequence ...................................................... 104
Erasing ..................................................................... 104
Operation During Code-Protect ............................... 107
Reading .................................................................... 103
Table Pointer
Table Pointer Boundaries ........................................ 102
Table Reads and Table Writes .................................. 99
Write Sequence ....................................................... 105
Writing ...................................................................... 105
Associated Registers, Receive ........................ 328
Associated Registers, Transmit ....................... 327
Reception ......................................................... 327
Transmission .................................................... 326
Extended Microcontroller ................................. 112
Microcontroller ................................................. 112
EECON1 and EECON2 ................................... 100
TABLAT (Table Latch) Register ....................... 102
TBLPTR (Table Pointer) Register .................... 102
Boundaries Based on Operation ...................... 102
Protection Against Spurious Writes ................. 107
Unexpected Termination .................................. 107
Write Verify ...................................................... 107
G
GOTO .............................................................................. 384
H
Hardware Multiplier .......................................................... 121
I
I/O Ports ........................................................................... 139
I
INCF ................................................................................ 384
INCFSZ ............................................................................ 385
In-Circuit Debugger .......................................................... 362
In-Circuit Serial Programming (ICSP) ...................... 349, 362
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ................................. 95, 97, 410
Indirect Addressing ............................................................ 93
INFSNZ ............................................................................ 385
Initialization Conditions for All Registers ...................... 63–69
Instruction Cycle ................................................................ 78
2
C Mode (MSSP) ............................................................ 269
Introduction .............................................................. 121
Operation ................................................................. 121
Performance Comparison ........................................ 121
Pin Capabilities ........................................................ 139
Acknowledge Sequence Timing .............................. 297
Associated Registers ............................................... 303
Baud Rate Generator .............................................. 290
Bus Collision
Clock Arbitration ...................................................... 291
Clock Rate w/BRG ................................................... 290
Clock Stretching ....................................................... 283
Clock Synchronization and the CKP Bit ................... 284
Effects of a Reset .................................................... 298
General Call Address Support ................................. 287
Master Mode ............................................................ 288
Multi-Master Communication, Bus Collision and Arbitra-
Multi-Master Mode ................................................... 298
Operation ................................................................. 274
Read/Write Bit Information (R/W Bit) ............... 274, 276
Registers ................................................................. 269
Serial Clock (SCKx/SCLx) ....................................... 276
Slave Mode .............................................................. 274
Sleep Operation ....................................................... 298
Stop Condition Timing ............................................. 297
and Standard PIC18 Instructions ............................. 410
BSR ........................................................................... 97
Clocking Scheme ....................................................... 78
Flow/Pipelining ........................................................... 78
During a Repeated Start Condition .................. 301
During a Stop Condition .................................. 302
10-Bit Slave Receive Mode (SEN = 1) ............ 283
10-Bit Slave Transmit Mode ............................ 283
7-Bit Slave Receive Mode (SEN = 1) .............. 283
7-Bit Slave Transmit Mode .............................. 283
Baud Rate Generator ...................................... 290
Operation ......................................................... 289
Reception ........................................................ 294
Repeated Start Condition Timing .................... 293
Start Condition Timing ..................................... 292
Transmission ................................................... 294
tion ................................................................... 298
Address Masking ............................................. 275
Addressing ....................................................... 274
Reception ........................................................ 276
Transmission ................................................... 276
© 2009 Microchip Technology Inc.
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