PIC18F96J65-I/PF Microchip Technology, PIC18F96J65-I/PF Datasheet - Page 240
![96KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm TRAY](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC18F96J65-I/PF
Manufacturer Part Number
PIC18F96J65-I/PF
Description
96KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(8 pages)
3.PIC18F66J65-IPT.pdf
(480 pages)
4.PIC18F66J65-IPT.pdf
(4 pages)
5.PIC18F66J65-IPT.pdf
(10 pages)
6.PIC18F96J60-IPT.pdf
(24 pages)
Specifications of PIC18F96J65-I/PF
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
96KB (48K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F96J65-I/PF
Manufacturer:
Microchip
Quantity:
251
Company:
Part Number:
PIC18F96J65-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F66J65-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- PIC18F66J65-IPT PDF datasheet #5
- PIC18F96J60-IPT PDF datasheet #6
- Current page: 240 of 480
- Download datasheet (8Mb)
PIC18F97J60 FAMILY
An example of how the entire assembled transmit
packet looks in memory is shown in Figure 18-9. To
construct and transmit a packet in this fashion:
1.
2.
3.
4.
5.
If a DMA operation was in progress while the TXRTS bit
was set, the module will wait until the DMA operation is
complete before attempting to transmit the packet. This
possible delay is required because the DMA and
FIGURE 18-9:
DS39762E-page 240
Set the ETXST Pointers to an appropriate
unused location in the buffer. This will be the
location of the per-packet control byte. In the
example, it would be 0120h. It is recommended
that an even address be used for the ETXST
Pointers.
Using EDATA and the EWRPT registers,
sequentially write the packet data to the Ether-
net buffer. In order, write the data for the
per-packet control byte, the destination address,
the source MAC address, the type/length and
the data payload.
Set the ETXND Pointers to point to the last byte
in the data payload. In the example, it would be
programmed to 0156h.
Clear the TXIF flag bit (EIR<3>), and set the
TXIE (EIE<3>) and ETHIE bits to enable an
interrupt when done (if desired).
Start the transmission process by setting the
TXRTS bit (ECON1<3>).
Buffer Pointers
ETXST = 0120h
ETXND = 0156h
SAMPLE TRANSMIT PACKET LAYOUT
Address
015Ch
015Dh
015Ah
015Bh
015Eh
0120h
0121h
0122h
0156h
0157h
0158h
0159h
tsv[23:16]
tsv[31:24]
tsv[39:32]
tsv[47:40]
tsv[55:48]
Memory
tsv[15:8]
data[m]
tsv[7:0]
data[1]
data[2]
0Eh
Status Vector
Data Packet
transmission engine share the same memory arbiter
channel. Similarly, if the DMAST bit is set after TXRTS
is already set, the DMA will wait until the TXRTS bit
becomes clear before doing anything.
While the transmission is in progress, the ETXST and
ETXND Pointers should not be modified. If it is
necessary to cancel the transmission, clear the TXRTS
bit.
When the packet is finished transmitting, or was
aborted due to an error/cancellation, several things
occur:
• The TXRTS bit is cleared.
• A 7-byte transmit status vector is written to the
• The TXIF flag is set
• An interrupt will be generated (if enabled)
• The ETXST and ETXND Pointers will not be
To check if the packet was successfully transmitted,
read the TXABRT bit. If it has been set, poll the BUFER
bit in addition to the various fields in the transmit status
vector to determine the cause. The transmit status
vector is organized as shown in Table 18-4. Multi-byte
fields are written in little-endian format.
Control
buffer at the location pointed to by the ETXND
Pointers + 1.
modified.
Description
PHUGEEN, PPADN,
PCRCEN and POVERRIDE
Destination Address,
Source Address,
Type/Length and Data
Status Vector
Written by the Hardware
Start of the Next Packet
© 2009 Microchip Technology Inc.
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