PIC18F96J65-I/PF Microchip Technology, PIC18F96J65-I/PF Datasheet - Page 153
![96KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm TRAY](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC18F96J65-I/PF
Manufacturer Part Number
PIC18F96J65-I/PF
Description
96KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(8 pages)
3.PIC18F66J65-IPT.pdf
(480 pages)
4.PIC18F66J65-IPT.pdf
(4 pages)
5.PIC18F66J65-IPT.pdf
(10 pages)
6.PIC18F96J60-IPT.pdf
(24 pages)
Specifications of PIC18F96J65-I/PF
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
96KB (48K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F96J65-I/PF
Manufacturer:
Microchip
Quantity:
251
Company:
Part Number:
PIC18F96J65-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F66J65-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- PIC18F66J65-IPT PDF datasheet #5
- PIC18F96J60-IPT PDF datasheet #6
- Current page: 153 of 480
- Download datasheet (8Mb)
TABLE 10-11:
TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
© 2009 Microchip Technology Inc.
PORTE
LATE
TRISE
LATA
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1:
RE5/AD13/
P1C
RE6/AD14/
P1B
RE7/AD15/
ECCP2/P2A
Legend:
Note 1:
Pin Name
Name
(4)
2:
3:
4:
5:
6:
Unimplemented on 64-pin devices; read as ‘0’.
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
EMB functions implemented on 100-pin devices only.
External memory interface I/O takes priority over all other digital and PSP I/O.
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin and 100-pin devices).
Unimplemented on 64-pin devices.
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (80-pin and 100-pin devices in
Microcontroller mode).
Unimplemented on 64-pin and 80-pin devices.
(4)
TRISE7
LATE7
RE7
RDPU
Bit 7
ECCP2
Function
AD13
AD14
AD15
P1C
P1B
P2A
PORTE FUNCTIONS (CONTINUED)
RE5
RE6
RE7
(1)
(1)
(1)
(3)
(3)
(5)
(1)
(1)
(1)
(5)
TRISE6
LATE6
RE6
REPU
Bit 6
Setting
TRIS
(1)
0
1
x
x
0
0
1
x
x
0
0
1
x
x
0
1
0
(1)
(1)
TRISE5
LATE5
LATA5
Bit 5
I/O
RE5
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Type
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
I/O
ST
ST
ST
ST
TRISE4
LATE4
LATA4
Bit 4
RE4
LATE<5> data output.
PORTE<5> data input; weak pull-up when REPU bit is set.
External memory interface, address/data bit 13 output.
External memory interface, data bit 13 input.
ECCP1 Enhanced PWM output, channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<6> data output.
PORTE<6> data input; weak pull-up when REPU bit is set.
External memory interface, address/data bit 14 output.
External memory interface, data bit 14 input.
ECCP1 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<7> data output.
PORTE<7> data input; weak pull-up when REPU bit is set.
External memory interface, address/data bit 15 output.
External memory interface, data bit 15 input.
ECCP2 compare output and PWM output; takes priority over
port data.
ECCP2 capture input.
ECCP2 Enhanced PWM output, channel A; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
PIC18F97J60 FAMILY
TRISE3
LATE3
LATA3
Bit 3
RE3
TRISE2
LATE2
LATA2
Bit 2
RE2
Description
TRISE1
LATE1
LATA1
Bit 1
RE1
(2)
(2)
(2)
TRISE0
LATE0
LATA0
Bit 0
DS39762E-page 153
RE0
(2)
(2)
(2)
on Page:
Values
Reset
66
66
65
66
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