PIC18F26K80-E/SP Microchip Technology, PIC18F26K80-E/SP Datasheet - Page 77
![ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SPDIP .300in TUBE](/photos/16/11/161110/pdip28_sml.jpg)
PIC18F26K80-E/SP
Manufacturer Part Number
PIC18F26K80-E/SP
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F26K80-E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC18F26K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F26K80-E/SP
Manufacturer:
SILICON
Quantity:
210
- Current page: 77 of 628
- Download datasheet (6Mb)
REGISTER 4-3:
2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CCP5MD
R/W-0
CCP5MD: CCP5 Module Disable bit
1 = The CCP5 module is disabled. All CCP5 registers are held in Reset and are not writable.
0 = The CCP5 module is enabled
CCP4MD: CCP4 Module Disable bit
1 = The CCP4 module is disabled. All CCP4 registers are held in Reset and are not writable.
0 = The CCP4 module is enabled
CCP3MD: CCP3 Module Disable bit
1 = The CCP3 module is disabled. All CCP3 registers are held in Reset and are not writable.
0 = The CCP3 module is enabled
CCP2MD: CCP2 Module Disable bit
1 = The CCP2 module is disabled. All CCP2 registers are held in Reset and are not writable.
0 = The CCP2 module is enabled
CCP1MD: ECCP1 Module Disable bit
1 = The ECCP1 module is disabled. All ECCP1 registers are held in Reset and are not writable.
0 = The ECCP1 module is enabled
UART2MD: EUSART2 Module Disable bit
1 = The USART2 module is disabled. All USART2 registers are held in Reset and are not writable.
0 = The USART2 module is enabled
UART1MD: EUSART1 Module Disable bit
1 = The USART1 module is disabled. All USART1 registers are held in Reset and are not writable.
0 = The USART1 module is enabled
SSPMD: MSSP Module Disable bit
1 = The MSSP module is disabled. All SSP registers are held in Reset and are not writable.
0 = The MSSP module is enabled
CCP4MD
R/W-0
PMD0: PERIPHERAL MODULE DISABLE REGISTER 0
W = Writable bit
‘1’ = Bit is set
CCP3MD
R/W-0
CCP2MD
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F66K80 FAMILY
CCP1MD
R/W-0
UART2MD
R/W-0
x = Bit is unknown
UART1MD
R/W-0
DS39977C-page 77
SSPMD
R/W-0
bit 0
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