PIC18F26K80-E/SP Microchip Technology, PIC18F26K80-E/SP Datasheet - Page 422
![ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SPDIP .300in TUBE](/photos/16/11/161110/pdip28_sml.jpg)
PIC18F26K80-E/SP
Manufacturer Part Number
PIC18F26K80-E/SP
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F26K80-E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC18F26K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F26K80-E/SP
Manufacturer:
SILICON
Quantity:
210
- Current page: 422 of 628
- Download datasheet (6Mb)
PIC18F66K80 FAMILY
REGISTER 27-31: BnEIDL: TX/RX BUFFER ‘n’ EXTENDED IDENTIFIER REGISTERS,
REGISTER 27-32: BnDm: TX/RX BUFFER ‘n’ DATA FIELD BYTE ‘m’ REGISTERS IN RECEIVE MODE
REGISTER 27-33: BnDm: TX/RX BUFFER ‘n’ DATA FIELD BYTE ‘m’ REGISTERS IN TRANSMIT MODE
DS39977C-page 422
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
BnDm7
BnDm7
R/W-x
R/W-x
EID7
R-x
These registers are available in Mode 1 and 2 only.
These registers are available in Mode 1 and 2 only.
These registers are available in Mode 1 and 2 only.
EID<7:0>: Extended Identifier bits
BnDm<7:0>: Receive Buffer n Data Field Byte m bits (where 0 n < 3 and 0 < m < 8)
Each receive buffer has an array of registers. For example, Receive Buffer 0 has 7 registers: B0D0 to
B0D7.
BnDm<7:0>: Transmit Buffer n Data Field Byte m bits (where 0 n < 3 and 0 < m < 8)
Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0
to TXB0D7.
BnDm6
BnDm6
R/W-x
R/W-x
EID6
R-x
LOW BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL<n>) = 1]
[0 n 5, 0 m 7, TXnEN (BSEL<n>) = 0]
[0 n 5, 0 m 7, TXnEN (BSEL<n>) = 1]
W = Writable bit
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
‘1’ = Bit is set
BnDm5
BnDm5
R/W-x
R/W-x
EID5
R-x
BnDm4
BnDm4
FEID4
R/W-x
R/W-x
R-x
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
BnDm3
BnDm3
R/W-x
R/W-x
EID3
R-x
(1)
(1)
BnDm2
BnDm2
R/W-x
R/W-x
EID2
R-x
2011 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
x = Bit is unknown
BnDm1
BnDm1
R/W-x
R/W-x
EID1
R-x
(1)
BnDm0
BnDm0
R/W-x
R/W-x
EID0
R-x
bit 0
bit 0
bit 0
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