PIC18F26K80-E/SP Microchip Technology, PIC18F26K80-E/SP Datasheet - Page 221
![ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SPDIP .300in TUBE](/photos/16/11/161110/pdip28_sml.jpg)
PIC18F26K80-E/SP
Manufacturer Part Number
PIC18F26K80-E/SP
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F26K80-E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC18F26K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F26K80-E/SP
Manufacturer:
SILICON
Quantity:
210
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For more details on selecting the optimum C1 and C2
for a given crystal, see the crystal manufacture’s appli-
cations information. The optimum value depends in
part on the amount of parasitic capacitance in the
circuit, which is often unknown. For that reason, it is
highly recommended that thorough testing and valida-
tion of the oscillator be performed after values have
been selected.
14.5.1
The SOSC oscillator is also available as a clock source
in power-managed modes. By setting the clock select
bits, SCS<1:0> (OSCCON<1:0>), to ‘ 01 ’, the device
switches to SEC_RUN mode and both the CPU and
peripherals are clocked from the SOSC oscillator. If the
IDLEN bit (OSCCON<7>) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in
“Power-Managed Modes”
Whenever the SOSC oscillator is providing the clock
source, the SOSC System Clock Status flag,
SOSCRUN (OSCCON2<6>), is set. This can be used
to determine the controller’s current clocking mode. It
can also indicate the clock source currently being used
by the Fail-Safe Clock Monitor.
If the Clock Monitor is enabled and the SOSC oscillator
fails while providing the clock, polling the SOCSRUN
bit will indicate whether the clock is being provided by
the SOSC oscillator or another source.
14.5.2
The SOSC oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity. This is especially true when
the oscillator is configured for extremely Low-Power
mode, SOSCSEL<1:0> (CONFIG1L<4:3>) = 01 .
The oscillator circuit, displayed in
be located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than V
If a high-speed circuit must be located near the oscillator,
it may help to have a grounded guard ring around the
oscillator circuit. The guard, as displayed in
could be used on a single-sided PCB or in addition to a
ground plane. (Examples of a high-speed circuit include
the ECCP1 pin, in Output Compare or PWM mode, or
the primary oscillator, using the OSC2 pin.)
2011 Microchip Technology Inc.
USING SOSC AS A
CLOCK SOURCE
SOSC OSCILLATOR LAYOUT
CONSIDERATIONS
.
SS
or V
Figure
DD
.
14-2, should
Section 4.0
Figure
14-3,
Preliminary
PIC18F66K80 FAMILY
FIGURE 14-3:
In the Low Drive Level mode, SOSCSEL<1:0> = 01 , it is
critical that RC2 I/O pin signals be kept away from the
oscillator circuit. Configuring RC2 as a digital output, and
toggling it, can potentially disturb the oscillator circuit,
even with a relatively good PCB layout. If possible, either
leave RC2 unused or use it as an input pin with a slew
rate limited signal source. If RC2 must be used as a
digital output, it may be necessary to use the Higher
Drive Level Oscillator mode (SOSCSEL<1:0> = 11 ) with
many PCB layouts.
Even in the Higher Drive Level mode, careful layout
procedures should still be followed when designing the
oscillator circuit.
In addition to dV/dt induced noise considerations, it is
important to ensure that the circuit board is clean. Even
a very small amount of conductive, soldering flux
residue can cause PCB leakage currents that can
overwhelm the oscillator circuit.
14.6
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
Note: Not drawn to scale.
Timer1 Interrupt
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
V
OSC1
RC0
V
OSC2
RC1
RC2
DD
SS
DS39977C-page 221
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