PIC18F26K80-E/SP Microchip Technology, PIC18F26K80-E/SP Datasheet - Page 134
![ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SPDIP .300in TUBE](/photos/16/11/161110/pdip28_sml.jpg)
PIC18F26K80-E/SP
Manufacturer Part Number
PIC18F26K80-E/SP
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F26K80-E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC18F26K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F26K80-E/SP
Manufacturer:
SILICON
Quantity:
210
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PIC18F66K80 FAMILY
6.6.3
The use of Indexed Literal Offset Addressing mode
effectively changes how the lower part of Access RAM
(00h to 5Fh) is mapped. Rather than containing just the
contents of the bottom part of Bank 0, this mode maps
the contents from Bank 0 and a user-defined “window”
that can be located anywhere in the data memory
space.
The value of FSR2 establishes the lower boundary of
the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described. (See
Bank”
addressing mode is shown in
FIGURE 6-10:
DS39977C-page 134
Example Situation:
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 Pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to
Access RAM (000h-05Fh).
Special Function Registers
at F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.
.) An example of Access Bank remapping in this
the
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
bottom
of
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL
OFFSET ADDRESSING
the
Figure
Section 6.3.2 “Access
FFFh
000h
05Fh
100h
120h
17Fh
200h
F00h
F60h
6-10.
Data Memory
Not Accessible
Bank 14
Bank 15
Window
through
Bank 2
Bank 0
Bank 1
SFRs
Preliminary
Remapping the Access Bank applies only to operations
using the Indexed Literal Offset mode. Operations that
use the BSR (Access RAM bit = 1 ) will continue to use
Direct Addressing as before. Any Indirect or Indexed
Addressing operation that explicitly uses any of the
indirect file operands (including FSR2) will continue to
operate as standard Indirect Addressing. Any instruc-
tion that uses the Access Bank, but includes a register
address of greater than 05Fh, will use Direct
Addressing and the normal Access Bank map.
6.6.4
Although the Access Bank is remapped when the
extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.
BSR IN INDEXED LITERAL
OFFSET MODE
2011 Microchip Technology Inc.
Bank 1 “Window”
Access Bank
SFRs
00h
5Fh
60h
FFh
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