PIC18F26K80-E/SP Microchip Technology, PIC18F26K80-E/SP Datasheet - Page 402
![ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SPDIP .300in TUBE](/photos/16/11/161110/pdip28_sml.jpg)
PIC18F26K80-E/SP
Manufacturer Part Number
PIC18F26K80-E/SP
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F26K80-E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC18F26K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F26K80-E/SP
Manufacturer:
SILICON
Quantity:
210
- Current page: 402 of 628
- Download datasheet (6Mb)
PIC18F66K80 FAMILY
REGISTER 27-3:
DS39977C-page 402
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5
bit 4-0
Note 1:
MDSEL1
R/W-0
2:
3:
(1)
These bits can only be changed in Configuration mode. See
This bit is used in Mode 2 only.
If FIFO is configured to contain four or less buffers, then the FIFO interrupt will trigger.
MDSEL<1:0>: Mode Select bits
00 = Legacy mode (Mode 0, default)
01 = Enhanced Legacy mode (Mode 1)
10 = Enhanced FIFO mode (Mode 2)
11 = Reserved
FIFOWM: FIFO High Water Mark bit
1 = Will cause FIFO interrupt when one receive buffer remains
0 = Will cause FIFO interrupt when four receive buffers remain
EWIN<4:0>: Enhanced Window Address bits
These bits map the group of 16 banked CAN SFRs into Access Bank addresses, 0F60-0F6Dh. The
exact group of registers to map is determined by the binary value of these bits.
Mode 0:
Unimplemented: Read as ‘ 0 ’
Mode 1, 2:
00000 = Acceptance Filters 0, 1, 2 and BRGCON2, 3
00001 = Acceptance Filters 3, 4, 5 and BRGCON1, CIOCON
00010 = Acceptance Filter Masks, Error and Interrupt Control
00011 = Transmit Buffer 0
00100 = Transmit Buffer 1
00101 = Transmit Buffer 2
00110 = Acceptance Filters 6, 7, 8
00111 = Acceptance Filters 9, 10, 11
01000 = Acceptance Filters 12, 13, 14
01001 = Acceptance Filter 15
01010 - 01110 = Reserved
01111 = RXINT0, RXINT1
10000 = Receive Buffer 0
10001 = Receive Buffer 1
10010 = TX/RX Buffer 0
10011 = TX/RX Buffer 1
10100 = TX/RX Buffer 2
10101 = TX/RX Buffer 3
10110 = TX/RX Buffer 4
10111 = TX/RX Buffer 5
11000 - 11111 = Reserved
MDSEL0
R/W-0
ECANCON: ENHANCED CAN CONTROL REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
FIFOWM
R/W-0
(2)
EWIN4
(1)
R/W-1
Preliminary
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
EWIN3
R/W-0
Register 27-1
EWIN2
R/W-0
(3)
to change to Configuration mode.
2011 Microchip Technology Inc.
x = Bit is unknown
EWIN1
R/W-0
EWIN0
R/W-0
bit 0
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