PIC18F26K80-E/SP Microchip Technology, PIC18F26K80-E/SP Datasheet - Page 425
![ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SPDIP .300in TUBE](/photos/16/11/161110/pdip28_sml.jpg)
PIC18F26K80-E/SP
Manufacturer Part Number
PIC18F26K80-E/SP
Description
ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F26K80-E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC18F26K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F26K80-E/SP
Manufacturer:
SILICON
Quantity:
210
- Current page: 425 of 628
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27.2.3.2
This section describes the message acceptance filters
and masks for the CAN receive buffers.
REGISTER 27-37: RXFnSIDH: RECEIVE ACCEPTANCE FILTER ‘n’ STANDARD IDENTIFIER FILTER
REGISTER 27-38: RXFnSIDL: RECEIVE ACCEPTANCE FILTER ‘n’ STANDARD IDENTIFIER FILTER
2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
R/W-x
SID10
R/W-x
SID2
2:
Registers, RXF6SIDH:RXF15SIDH, are available in Mode 1 and 2 only.
Registers, RXF6SIDL:RXF15SIDL, are available in Mode 1 and 2 only.
In Mode 0, this bit must be set/cleared as required, irrespective of corresponding mask register value.
Message Acceptance Filters
and Masks
SID<10:3>: Standard Identifier Filter bits (if EXIDEN = 0 )
Extended Identifier Filter bits, EID<28:21> (if EXIDEN = 1 ).
SID<2:0>: Standard Identifier Filter bits (if EXIDEN = 0 )
Extended Identifier Filter bits, EID<20:18> (if EXIDEN = 1 ).
Unimplemented: Read as ‘ 0 ’
EXIDEN: Extended Identifier Filter Enable bit
1 = Filter will only accept extended ID messages
0 = Filter will only accept standard ID messages
Unimplemented: Read as ‘ 0 ’
EID<17:16>: Extended Identifier Filter bits
R/W-x
R/W-x
SID9
SID1
REGISTERS, HIGH BYTE [0 n 15]
REGISTERS, LOW BYTE [0 n 15]
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-x
R/W-x
SID8
SID0
R/W-x
SID7
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
PIC18F66K80 FAMILY
EXIDEN
(2)
R/W-x
R/W-x
SID6
(1)
(1)
(2)
R/W-x
SID5
U-0
—
x = Bit is unknown
x = Bit is unknown
R/W-x
R/W-x
EID17
SID4
DS39977C-page 425
EID16
R/W-x
R/W-x
SID3
bit 0
bit 0
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