DJLXT972ALC.A4 Cortina Systems Inc, DJLXT972ALC.A4 Datasheet - Page 9

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DJLXT972ALC.A4

Manufacturer Part Number
DJLXT972ALC.A4
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of DJLXT972ALC.A4

Lead Free Status / RoHS Status
Not Compliant
LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
Cortina Systems
Added
Modified
Added
Clock Requirements: Modified language under Clock Requirements heading.
I/O Characteristics REFCLK (table): Changed values for Input Clock Duty Cycle under Min from 40 to 35 and under Max from 60
to 65.
Initial Release.
Table 53 “Digital Config Register (Address
Section 8.0, “Product Ordering
Table 54 “Transmit Control Register #2 (Address
®
LXT972A Single-Port 10/100 Mbps PHY Transceiver
Information”.
Revision Date: 15 January 2001
Revision Date: 01 January 2001
Revision Date: 06 August 2002
26)”.
Revision 003
Revision 002
Revision 001
30)”.
Revision History
Page 9

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