DJLXT972ALC.A4 Cortina Systems Inc, DJLXT972ALC.A4 Datasheet - Page 24

• Manufacturer Part Number: DJLXT972ALC.A4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT972ALC.A4

• Lead Free Status / RoHS Status: Not Compliant

LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
5.2.3.1.1
5.2.3.1.2
Figure 3
Figure 4
5.2.3.1.3
Cortina Systems
Some registers are required and their functions are defined by the IEEE 802.3 standard.
The LXT972A PHY also supports additional registers for expanded functionality. The
LXT972A PHY supports multiple internal registers, each of which is 16 bits wide. Specific
register bits are referenced using an “X.Y” notation, where X is the register number (0-31)
and Y is the bit number (0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of
this interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read
and write operations are disabled and the Hardware Control Interface provides primary
configuration control. When MDDIS is Low, the MDIO port is enabled for both read and
write operations and the Hardware Control Interface is not used.
MDIO Addressing
The MDIO addressing protocol allows a controller to communicate with multiple PHYs.
Pin ADDR0 determines the PHY device address that is selected as follows.
MDIO Frame Structure
The physical interface consists of a data line (MDIO) and clock line (MDC). The frame
structure is shown in
MDIO Interface timing is given in
Management Interface Read Frame Structure
Management Interface Write Frame Structure
MII Interrupts
Figure 5 shows the MII interrupt logic.
pin (MDINT_L) and two dedicated interrupt registers, Register 18 and Register 19.
®
MDIO
(Read)
(Write)
• Connect pin ADDR0 low to get PHY address 0.
• Connect pin ADDR0 high to get PHY address 1.
MDC
• Register 18 provides interrupt enable and mask functions. Setting register bit 18.1 = 1
LXT972A Single-Port 10/100 Mbps PHY Transceiver
MDIO
MDC
High Z
enables the device to request interrupt via the MDINT_L pin. An active Low on this pin
Idle
Preamble
32 "1"s
Preamble
32 "1"s
0
0
ST
ST
1
1
Figure 3
1
0
Op Code
Op Code
1
0
Write
and
A4
A4
PHY Address
PHY Address
Section 7.0, Electrical Specifications.
Figure 4
A3
A3
The LXT972A PHY provides a hardware interrupt
A0
A0
Write
R4
R4
(Read and Write).
Register Address
Register Address
R3
R3
R0
R0
1
Z
Around
Around
Turn
Turn
0
0
D15
D15
5.2 Network Media / Protocol
D15
D14
D14
Data
Read
D14
Data
D1
D1
D1
D0
D0
B3490-01
Idle
Idle
B3489-01
Support
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