DJLXT972ALC.A4 Cortina Systems Inc, DJLXT972ALC.A4 Datasheet - Page 55

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DJLXT972ALC.A4

Manufacturer Part Number
DJLXT972ALC.A4
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of DJLXT972ALC.A4

Lead Free Status / RoHS Status
Not Compliant
LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
Figure 22
Cortina Systems
100BASE-TX Receive Timing
®
• Figure 25, 10BASE-T Jabber and Unjabber Timing, on page 58
• Figure 26, 10BASE-T SQE (Heartbeat) Timing, on page 58
• Figure 27, Auto-Negotiation and Fast Link Pulse Timing, on page 59
• Figure 28, Fast Link Pulse Timing, on page 59
• Figure 29, MDIO Input Timing, on page 60
• Figure 30, MDIO Output Timing, on page 60
• Figure 31, Power-Up Timing, on page 61
• Figure 32, RESET_L Pulse Width and Recovery Timing, on page 61
LXT972A Single-Port 10/100 Mbps PHY Transceiver
Note: Timing diagram depicts 4B mode.
RXD[3:0]
RX_CLK
RX_DV
CRS
COL
TPI
0 ns
t6
t4
t3
250 ns
t5
t7
t1
7.2 AC Timing Diagrams and
t2
B3492-03
Parameters
Page 55

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