DJLXT972ALC.A4 Cortina Systems Inc, DJLXT972ALC.A4 Datasheet - Page 17

• Manufacturer Part Number: DJLXT972ALC.A4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT972ALC.A4

• Lead Free Status / RoHS Status: Not Compliant

LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
.
Table 6
Table 7
Table 8
Cortina Systems
MII Controller Interface Signal Descriptions
LXT972A: Network Interface Signal Descriptions
LXT972A: Standard Bus and Interface Signal Descriptions
®
LXT972A Single-Port 10/100 Mbps PHY Transceiver
LQFP
LQFP
LQFP
Pin#
Pin#
Pin#
43
42
64
19
20
23
24
12
3
MDINT_L
Symbol
Symbol
Symbol
ADDR0
MDDIS
TPON
MDIO
TPOP
MDC
TPIP
TPIN
Type
Type
Type
OD
I/O
O
I
I
I
I
Management Data Disable.
When MDDIS is High, the MDIO is disabled from read and write
operations.
When MDDIS is Low at power-up or reset, the Hardware Control
Interface pins control only the initial or “default” values of their respective
register bits.
After the power-up/reset cycle is complete, bit control reverts to the
MDIO serial channel.
Management Data Clock.
Clock for the MDIO serial data channel.
Maximum frequency is 8 MHz.
Management Data Input/Output.
Bidirectional serial data channel for PHY/STA communication.
Management Data Interrupt.
When register bit 18.1 = 1, a Low output on this active-low pin indicates a
status change.
Interrupt is cleared by reading Register 19.
Twisted-Pair Outputs, Positive and Negative.
During 100BASE-TX or 10BASE-T operation, TPOP/N pins drive IEEE
802.3 compliant pulses onto the line.
Twisted-Pair Inputs, Positive and Negative.
During 100BASE-TX or 10BASE-T operation, TPIP/N pins receive
differential 100BASE-TX or 10BASE-T signals from the line.
Address 0.
Sets device address.
Signal Description5
Signal Description
Signal Description
4.0 Signal Descriptions
Page 17