DJLXT972ALC.A4 Cortina Systems Inc, DJLXT972ALC.A4 Datasheet - Page 28

• Manufacturer Part Number: DJLXT972ALC.A4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT972ALC.A4

• Lead Free Status / RoHS Status: Not Compliant

LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
5.4.4
Table 13
5.5
Note:
Cortina Systems
1. L = Low, and H = High. For LED/CFG pin assignments, see
Auto-Neg.
Disabled
Enabled
Desired Mode
(Mbps)
Speed
10/100
Only
100
100
10
For pin settings used during a hardware reset, see
Settings. During a hardware reset, configuration settings for auto-negotiation and speed
are read in from pins, and register information is unavailable for 1 ms after de-assertion of
the reset.
Hardware Configuration Settings
The LXT972A PHY provides a hardware option to set the initial device configuration. As
listed in
for which provide control bits.
Hardware Configuration Settings
Establishing Link
Figure 6
When a link is established by using parallel detection, the LXT972A PHY sets the duplex
mode to half-duplex, as defined by the IEEE 802.3 standard.
®
LXT972A Single-Port 10/100 Mbps PHY Transceiver
Full or Half
Half Only
Full/Half
Duplex
Table 13,
Half
Half
Half
Full
Full
shows an overview of link establishment for the LXT972A PHY.
H
H
H
H
1
L
L
L
L
Settings
LED/CFG
the hardware option uses the hardware configuration pins, the settings
Pin
H
H
H
H
2
L
L
L
L
H
H
H
H
1
3
L
L
L
L
Auto-
Neg.
0.12
0
1
Control Register
Speed
0.13
Section 3.0, Ball and Pin Assignments
0
0
1
1
1
1
1
1
Duplex
Full-
0.8
Resulting register bit Values
1
0
1
0
1
0
1
0
Section 5.4.4, Hardware Configuration
BASE-TX
Duplex
Full-
100
4.8
Auto-Negotiation Advertisement
0
1
0
1
BASE-
Auto-Negotiation
100
4.7
Advertisement
TX
1
1
1
1
Register
N/A
5.5 Establishing Link
BASE-T
Duplex
Full-
4.6
10
0
0
0
1
BASE-T
Page 28
4.5
10
0
0
1
1