ICS1892Y IDT, Integrated Device Technology Inc, ICS1892Y Datasheet - Page 70

• Manufacturer Part Number: ICS1892Y
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS1892Y

• Lead Free Status / RoHS Status: Not Compliant

8.3.12 Jabber Detect (bit 1.1)
8.3.13 Extended Capability (bit 1.0)
ICS1892, Rev. D, 2/26/01
The purpose of this bit is to allow an STA to read this bit to determine if the ICS1892 detects a Jabber
condition.
The ISO/IEC specification defines the requirements for detection of a Jabber condition.To detect a Jabber
condition, the ICS1892 must first enable its Jabber Detection function, which is controlled by the Jabber
Inhibit bit in the 10Base-T Operations register (bit 18.5). When bit 18.5 is logic:
•
•
Bit 1.1 is a latching high (LH) bit. (For more information on latching high and latching low bits, see
8.1.4.1, “Latching High Bits”
The STA reads bit 1.0 to determine if the ICS1892 has an extended register set. In the ICS1892 this bit is
always logic one, indicating that it has extended registers.
Zero, the ICS1892 disables Jabber Detection
One, the ICS1892 enables Jabber Detection. In this case, when the ICS1892 detects a Jabber condition,
it does the following:
– It sets bit 1.2 to logic one.
– It sets the Jabber Detect bit (bit 1.1 in the Status Register, and mirrored as bit 17.2 in the QuickPoll
ICS1892 Data Sheet
Detailed Status Register) to logic one.
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
and
Section 8.1.4.2, “Latching Low
70
Bits”.)
Chapter 8 Management Register Set
February 26, 2001
Section