ICS1892Y IDT, Integrated Device Technology Inc, ICS1892Y Datasheet - Page 55

• Manufacturer Part Number: ICS1892Y
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS1892Y

• Lead Free Status / RoHS Status: Not Compliant

7.6 Functional Block: Management Interface
7.6.1 Management Register Set Summary
7.6.2 Management Frame Structure
ICS1892, Rev. D, 2/26/01
As part of the MII, the ISO/IEC 8802-3 standard specifies a two-wire serial management interface and
protocol. This interface is used to exchange control, status, and configuration information between the
Station Management entity (STA) and the physical layer device (PHY). For using this management
interface, the ISO/IEC standard specifies the following:
•
•
•
The ICS1892 implementation of the management interface complies fully with the ISO/IEC standard. It
provides a bi-directional data pin (MDIO) along with a clock (MDC) for synchronizing the data transfers.
These pins remain active in all MAC/Repeater Interface modes (that is, the 10/100 MII, 100M Symbol, 10M
Serial, and Link Pulse interface modes).
The ICS1892 implements a Management Register set that adheres to the ISO/IEC standard. This register
set (discussed in detail in
and Status registers as well as the ICS-specific Extended registers.
The Management Interface is a bi-directional serial interface to exchange configuration, control, and status
data between a PHY such as the ICS1892 and the STA. The PHY and STA exchange data by using the
defined register set. The STA initiates all transactions.
The ISO/IEC specification defines a Management Frame Structure for the serial data stream. The ICS1892
complies with the defined frame structure and protocol.
Structure.
Note:
Table 7-2. Management Frame Structure Summary
PRE
SFD
OP
PHYAD
REGAD
TA
DATA
A set of registers
The frame structure
The protocol
Acronym
ICS1892
The Management Frame Structure starts from and returns to an IDLE condition. However, the
IDLE periods are not part of the Management Frame Structure.
Preamble (Bit 1.6)
Start of Frame
Operation Code
PHY Address (Bits 16.10:6)
Register Address
Turnaround
Data
Frame Field
(Section 7.6.1, “Management Register Set
(Section 7.6.2, “Management Frame
Frame Function
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
Chapter 8, “Management Register
55
11..11
01
10/01 (read/write)
AAAAA
RRRRR
Z0/10 (read/write)
DDD..DD
Table 7-2
Data
Structure”)
Set”) includes the mandatory ‘Basic’ Control
Summary”)
summarizes the Management Frame
32 ones
2 bits
2 bits
5 bits
5 bits
2 bits
16 bits
Comment
Chapter 7 Functional Blocks
February 26, 2001