HBLXT9761HC.C4 Intel, HBLXT9761HC.C4 Datasheet - Page 60

HBLXT9761HC.C4

Manufacturer Part Number
HBLXT9761HC.C4
Description
Manufacturer
Intel
Datasheet

Specifications of HBLXT9761HC.C4

Lead Free Status / RoHS Status
Not Compliant
LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII
60
MDIO setup before MDC, sourced by
STA
MDIO hold after MDC,
sourced by STA
MDC to MDIO output delay, sourced
by PHY
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
Figure 34. MDIO Write Timing (MDIO Sourced by MAC)
Figure 35. MDIO Read Timing (MDIO Sourced by PHY)
Table 30. MDIO Timing Parameters
Parameter
MDIO
MDIO
MDC
MDC
Sym
t1
t2
t3
t3
Min
10
10
10
1
1
t1
Typ
130
1
t2
Max
300
Units
ns
ns
ns
ns
ns
ns
MDC = 2.5 MHz
MDC = 8 MHz
MDC = 2.5 MHz
MDC = 8 MHz
MDC = 2.5 MHz
MDC = 8 MHz
Test Conditions
Datasheet

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