HBLXT9761HC.C4 Intel, HBLXT9761HC.C4 Datasheet - Page 38

• Manufacturer Part Number: HBLXT9761HC.C4
• Manufacturer: Intel

Specifications of HBLXT9761HC.C4

• Lead Free Status / RoHS Status: Not Compliant

LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII
2.8.2
2.8.3
2.8.3.1
2.8.4
2.9
2.9.1
2.9.2
38
Dribble Bits
The LXT97x1 device handles dribbles bits in all modes. If between 1-4 dribble bits are received,
the nibble will be passed across the RMII, padded with 1s if necessary. If between 5-7 dribble bits
are received, the second nibble will not be sent onto the RMII bus.
Link Test
In 10T mode, the LXT97x1 always transmit link pulses. If the link test function is enabled, it
monitors the connection for link pulses. Once link pulses are detected, data transmission will be
enabled and will remain enabled as long as either the link pulses or data transmission continue. If
the link pulses stop, the data transmission will be disabled.
If the link test function is disabled, the LXT97x1 will transmit to the connection regardless of
detected link pulses. The link test function can be disabled by setting bit 16.14 = 1.
Link Failure
Link failure occurs if Link Test is enabled and link pulses or packets stop being received. If this
condition occurs, the LXT97x1 returns to the auto-negotiation phase if auto-negotiation is enabled.
Jabber
If a transmission exceeds the jabber timer, the LXT97x1 will disable the transmit and loopback
functions. The RMII does not include a Jabber pin, however the MAC may read Register 1 to
determine Jabber status.
The LXT97x1 automatically exits jabber mode after the unjab time has expired. This function can
be disabled by setting bit 16.10 = 1.
Monitoring Operations
Monitoring Auto-Negotiation
Auto-negotiation can be monitored as follows:
Serial LED Functions
The LXT97x1 provide eight serial LED outputs (LEDS7:0) which may be attached to external
HC595-type shift registers (refer to
data into the 595’s internal shift register. The LEDLATCH signal is used to load data from the
595’s internal shift register to the 595’s internal storage register. The LXT97x1 drives the LEDSn
and LEDLATCH outputs on the falling edge of LEDCLK. All serial LEDs will be stretched in
accordance with 20.1 & 20.3:2.
•
•
Bits 1.2 and 17.10 = 1 once the link is established.
Additional bits in Register 1 (refer to
on page
71) can be used to determine the link operating conditions and status.
Figure 25 on page
Table 36 on page
51). The LEDCLK signal is used to shift
65) and Register 17 (refer to
Datasheet
Table 45