HBLXT9761HC.C4 Intel, HBLXT9761HC.C4 Datasheet - Page 15

• Manufacturer Part Number: HBLXT9761HC.C4
• Manufacturer: Intel

Specifications of HBLXT9761HC.C4

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
1. Type Column Coding: I = Input, O = Output, OD = Open Drain
2. The LXT97x1 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
3. Ports 6 and 7 are available only on the LXT9781. These pins are not bonded out on the LXT9761.
1. Type Column Coding: I = Input, O = Output.
2. Ports 6 and 7 are available only on the LXT9781. These pins are not bonded out on the LXT9761.
9761 Pin#
where X is the register number (0-32) and Y is the bit number (0-15).
PQFP
Table 1. LXT97x1 RMII Signal Descriptions (Continued)
PQFP
Table 2. LXT97x1 Signal Detect/TP Select Signal Descriptions
9761
Pin#
101
100
161
160
159
99
70
71
84
85
–
–
PQFP
PQFP
101
100
162
161
160
159
99
98
70
71
84
85
9781 Pin#
9781 Pin#
PBGA
PBGA
U13
U14
U15
C16
C17
V16
B17
A17
U12
Y12
W8
V8
Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781
SD0/TP0
SD1/TP1
SD2/TP2
SD3/TP3
SD4/TP4
SD5/TP5
SD6/TP6
SD7/TP7
MDC
MDIO
MDINT
MDDIS
Symbol
Symbol
RMII Control Interface Pins
Type
Type
OD
I/O
I
I
I
1
1
Signal Detect - Ports 0 - 7. Tying the SD/TPn pins High or to
a PECL input sets bit 16.0 = 1 and the respective port is
forced to FX mode. In the absence of an active link, the pin
must be pulled High to enable loopback in FX mode. Do not
enable Auto-Negotiation if FX mode is selected.
The SD/TPn pins have internal pull-downs. When not using
FX mode, SD/TPn pins should be tied to GNDA.
TP Select - Ports 0 - 7. Tying the SD/TPn pins Low sets bit
16.0 = 0 and forces the respective port to TP mode.
Management Data Clock. Clock for the MDIO serial data
channel.
Maximum frequency is 8 MHz.
Management Data Input/Output. Bidirectional serial data
channel for PHY/STA communication.
Management Data Interrupt. When bit 18.1 = 1, an active
Low output on this pin indicates status change. Interrupt is
cleared when Register 19 is read.
Management Disable.
When MDDIS is High, the MDIO is disabled from read and
write operations.
When MDDIS is Low at power up or reset, the Hardware
Control Interface pins control only the initial or “default”
values of their respective register bits. After the power-up/
reset cycle is complete, bit control reverts to the MDIO serial
channel.
Signal Description
Signal Description
2, 3
2
15