HBLXT9761HC.C4 Intel, HBLXT9761HC.C4 Datasheet - Page 54
HBLXT9761HC.C4
Manufacturer Part Number
HBLXT9761HC.C4
Description
Manufacturer
Intel
Datasheet
1.HBLXT9761HC.C4.pdf
(78 pages)
Specifications of HBLXT9761HC.C4
Lead Free Status / RoHS Status
Not Compliant
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII
54
Rise/fall time symmetry
Duty cycle distortion
Overshoot
Peak differential output voltage
(single ended)
Signal rise/fall time
Jitter (measured differentially)
Peak differential input voltage
Common mode input range
Peak differential output voltage
Link transmit period
Transmit timing jitter added by the
MAU and PLS sections
Link min receive timer
Link max receive timer
Time link loss receive
Differential squelch threshold
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Measured at the line side of the transformer, line replaced by 100 (+/-1%) resistor.
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Measured at the line side of the transformer, line replaced by 100 (+/-1%) resistor.
3. Parameter is guaranteed by design; not subject to production testing.
4. IEEE 802.3 specifies maximum jitter addition at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU.
5. After line model specified by IEEE 802.3 for 10BASE-T MAU
Table 20. 100BASE-TX Transceiver Characteristics (Continued)
Table 21. 100BASE-FX Transceiver Characteristics
Table 22. 10BASE-T Transceiver Characteristics
Parameter
Parameter
Parameter
3, 4
TLRmax
TLRmin
Sym
V
TLL
V
V
T
Sym
Sym
OP
–
–
V
DS
T
V
V
CMIR
RFS
–
OP
RF
–
O
IP
Min
–
–
–
Min
2.2
0.55
50
50
Min
0.6
8
0
2
–
–
–
–
Transmitter
Transmitter
Typ
Receiver
Receiver
–
–
–
Typ
1
390
2.5
64
64
Typ
–
–
4
–
–
–
–
–
1
± 0.5
1
Max
0.5
5
Max
150
150
2.8
24
11
7
–
V
Units
CC
ns
ns
%
Max
1.5
1.4
1.5
1.9
- 0.7
mV Peak
Offset from 16ns pulse width at 50% of
pulse peak
Units
ms
ms
ms
ms
ns
V
Units
ns
ns
V
V
V
5 MHz square wave input
Test Conditions
10 <–> 90%
Note 2
Test Conditions
–
Test Conditions
Note 2
Note 5
–
–
–
–
–
–
–
–
Datasheet
2.0 pF load
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