TS81102G0VTP E2V, TS81102G0VTP Datasheet - Page 34

• Manufacturer Part Number: TS81102G0VTP
• Manufacturer: E2V

Specifications of TS81102G0VTP

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 110C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Addendum
Synchronous
Reset Operation
SETUP and HOLD
Timings
Operation in DR Mode
Figure 26. Synchronous Reset Operation in DR Mode, 1:4 ratio, 1GHz (Full Speed) – Principle of Operation
34
TS81102G0
Sync_RESET
This section has been added to the description of the device for better understanding of the
synchronous reset operation. It puts particular stress on the setup and hold times defined in
the switching characteristics table (Table 5), linked with the device performances when used
at full speed (2 Gsps).
It first describes the operation of the synchronous reset in case the DMUX is used in DR mode
and then when used in the DR/2 mode.
As a reminder, the synchronous reset has to be a signal frequency of Fs/8N in 1:8 ratio or
Fs/4N in 1:4 ratio, where N is an integer.
The effect of the synchronous reset is to ensure that at each new port selection cycle, the first
port to be selected is port A. The synchronous reset ensures the internal cyclic synchroniza-
tion of the device during operation. It is also highly recommended in the case of multichannel
applications using 2 synchronized DMUXs.
The setup and hold times for the reset are defined as follows:
•
Required delay between the rising edge of the reset and the rising edge of the clock to ensure
that the reset will be taken into account at the next clock edge. If the reset rising edge occurs
at less than this setup time, it will be taken into account only at the second next rising edge of
the clock.
A margin of ± 100ps has to be added to this setup time to compensate for the delays from the
drivers and lines.
•
Minimum duration of the reset signal at a high level to be taken into account by the DMUX.
This means that the reset signal has to satisfy 2 requirements: a frequency of Fs/8N or Fs/4N
(N is an integer) depending on the ratio and a duty cycle such that it is high during at least the
hold time.
In DR mode, the DMUX input clock can run at up to 2 GHz in 1:8 ratio or 1 GHz in 1:4 ratio.
Both cases are described in the following timing diagrams.
SETUP from SynchReset to Clkin:
HOLD from Clkin and SynchReset:
Fs
2105C–BDC–11/03