TS81102G0VTP E2V, TS81102G0VTP Datasheet - Page 15

• Manufacturer Part Number: TS81102G0VTP
• Manufacturer: E2V

Specifications of TS81102G0VTP

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 110C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table 5. Switching Performances (Continued)
Notes:
2105C–BDC–11/03
Parameter
Setup time from Bist to Clkln
Rise/fall time for (10% – 90%)
ADC Delay Adjust
Input frequency
Input pulse width (high)
Input pulse width (low)
Input rise/fall time
Output rise/fall time
Data output delay (typical delay adjust setting)
Output delay drift with temperature
Output delay uncertainly
1. TCPD is tuned with DMUXDelAdjCtrl: TCPD = 981 ± 250 ps.
2. TCPD is tuned with DMUXDelAdjCtrl: TCPD = 1084 ± 250 ps.
3. TSSR depends on DMUXDelAdjCtrl: TSSR = -580 ± 250 ps. TSSR < 0 because of Clock Path internal delay.
4. TSSR depends on DMUXDelAdjCtrl: TSSR = -477 ± 250 ps. TSSR < 0 because of Clock Path internal delay.
5. THSR depends on DMUXDelAdjCtrl: THSR = 780 ± 250 ps.
6. THSR depends on DMUXDelAdjCtrl: THSR = 677 ± 250 ps.
7. TSCKIN depends on DMUXDelAdjCtrl: TSCKIN = -794 ± 250 ps. TSCKIN < 0 because of Clock Path internal delay.
8. TSCKIN depends on DMUXDelAdjCtrl: TSCKIN = -691 ± 250 ps. TSCKIN < 0 because of Clock Path internal delay.
9. THCKIN depends on DMUXDelAdjCtrl: THCKIN = 994 ± 250 ps.
10. THCKIN depends on DMUXDelAdjCtrl: THCKIN = 891 ± 250 ps.
11. TOD depends on DMUXDelAdjCtrl: TOD = 1820 ± 250 ps. TOD is given for ECL 50 /2 pFoutput load.
12. TOD depends on DMUXDelAdjCtrl: TOD = 1717 ± 250 ps. TOD is given for ECL 50 /2 pFoutput load.
13. TPD is the number of Clkln clock cycle from selection of Port A to selection of Port H in 1:8 conversion mode, and from
14. TROD and TFOD are given for ECL 50 /2 pF output load. In TTL mode, the TROD and TFOD are twice the ones for ECL.
15. TDRF depends on DMUXDelAdjCtrl: TDRF = 1856 ± 250 ps. It is given for ECL 50 /2 pF output load.
16. TDRF depends on DMUXDelAdjCtrl: TDRF = 1753 ± 250 ps. It is given for ECL 50 /2 pF output load.
17. TDRR depends on DMUXDelAdjCtrl: TDRR = 1858 ± 250 ps. It is given for ECL 50 /2 pF output load.
18. TDRR depends on DMUXDelAdjCtrl: TDRR = 1725 ± 250 ps. It is given for ECL 50 /2 pF output load.
19. TARDR is given for ECL 50 /2 pF output load.
20. TSRDR is given for ECL 50 /2 pF output load. It is minimum value since RstSync clock is synchronized with Clkln clock.
21. TRDR and TFDR are given for ECL 50 /2 pF output load.
22. THBIST depends on the configuration of the DMUX. There must be enough Clkln clock cycles to have all the 512 codes,
23. With transmission line (ZO = 50 ) and output load R = 50 ; C = 2 pF.
24. Without output load.
25. With transmission line (ZO = 50 ) and output load R = 50 ; C = 2 pF.
selection of Port A to selection of Port D in 1:4 conversion mode. It is the maximum number of Clkln clock cycle, or pipeline
delay, that a data has to stay in the DMUX before being sorted out. This maximum delay occurs for the data sent to Port A.
For instance, the data sent to Port H goes directly from the input to the Port H, and its pipeline is 0. But even for this data,
there is an additional delay due to physical propagation time in the DMUX.
(For other termination topology, apply proper derating value 50 ps/pF in ECL, 100 ps/pF in TTL mode.)
(see different Timing Diagrams).
TROADA/
TC1ADA
TC2ADA
TRIADA/
TFOADA
TRBIST/
Symbol
TFIADA
TSBIST
TFBIST
FMADA
JITADA
TADAT
TADA
Level
Test
–
–
–
–
–
–
–
–
–
–
1000
Min
100
100
90
90
–
2
–
–
–
–
–
–
Value
1000
Typ
150
150
145
104
784
896
2.5
30
–
–
–
–
Max
2.2
–
–
–
–
–
–
–
–
–
–
–
–
TS81102G0
ps/ C
Unit
GHz
ps
ps
ps
ps
ps
ps
ps
ps
Note
(23)
(24)
(25)
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