TS81102G0VTP E2V, TS81102G0VTP Datasheet - Page 19

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TS81102G0VTP

Manufacturer Part Number
TS81102G0VTP
Description
Manufacturer
E2V
Datasheet

Specifications of TS81102G0VTP

Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
-40C to 110C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Timing Diagrams with
Synchronous Reset
Figure 16. Synchronous Reset, 1:8 Ratio, DR Mode
2105C–BDC–11/03
(not available out of the DEMUX)
Internal Port Selection
SyncReset
Following is an example of the Synchronous Reset’s utility in case of de-synchronization of the
DMUX output port selection. The de-synchronization event happens after the selection of Port
D.
DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln’s internal propagation delay
TCPD. After selection of Port C, instead of selecting Port D, the de-synchronization makes the
port selection to restart on Port A. Since Port H was not selected, the data is not output to the
ports but the last data (d1 to d8) is latched until the next selection of Port H. d9 to d16 are lost.
The synchronous Reset ensures a re-synchronization of the port selection.
Example of the Synchronous Reset’s utility in case of de-synchronization of the DMUX output
port selection. The de-synchronization event happens after the selection of Port D.
DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln’s internal propagation delay
TCPD. After selection of Port C, instead of selecting Port D, the de-synchronization makes the
port selection to restart on Port A. Since Port H was not selected, the data is not output to the
ports but the last data (d1 to d4) is latched until the next selection of Port H. d5 to d8 are lost.
The synchronous Reset ensures a re-synchronization of the port selection.
G[0..9]
A[0..9]
B[0..9]
C[0..9]
D[0..9]
E[0..9]
H[0..9]
F[0..9]
I[0..9]
Clkn
DR
d0
A
d1
B
TDRR
d2
C
d3
D
d4
E
d5
F
TDRF
d6
TOD
G
TSSR
TCPD
d7
H
THSR
d8
A
d9 d10 d11
B
C
Period of uncertainty due to desynchronization
A
d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27
B
C
TSRDR
D
TSSR
d1
d2
d3
d4
d5
d6
d7
d8
E
THSR
A
B
TDRR
C
D
E
F
TDRF
TOD
G
TSSR
TCPD
H
THSR
A
TS81102G0
B
d17
d18
d19
d20
d21
d22
d23
d24
C
D
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