TS81102G0VTP E2V, TS81102G0VTP Datasheet - Page 17

• Manufacturer Part Number: TS81102G0VTP
• Manufacturer: E2V

Specifications of TS81102G0VTP

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 110C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Timing Diagrams with
Asynchronous Reset
Figure 12. Start with Asynchronous Rest, 1:8 Ratio, DR Mode
Figure 13. Start with Asynchronous Rest, 1:8 Ratio, DR/2 Mode
2105C–BDC–11/03
(not available out of the DEMUX)
(not available out of the DEMUX)
Internal Port Selection
Internal Port Selection
ASyncReset
ASyncReset
G[0..9]
G[0..9]
A[0..9]
B[0..9]
C[0..9]
D[0..9]
E[0..9]
H[0..9]
A[0..9]
B[0..9]
C[0..9]
D[0..9]
E[0..9]
H[0..9]
F[0..9]
F[0..9]
I[0..9]
I[0..9]
Clkn
Clkn
DR
DR
With a nominal tuning of DMUXDelAdj at a frequency of 2 GHz, d1 and d2 data is lost because
of the internal clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins
to obtain good setup and hold times between Clkln and the data.
With a nominal tuning of DMUXDelAdj at 2 GHz, d1 and d2 data is lost because of the internal
clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins to obtain
good setup and hold times between Clkln and the input data. This timing diagram does not
change with the opposite phase of Clkln.
TARDR
TRAR
TRAR
TARDR
PWAR
PWAR
TFAR
TFAR
A
A
d1
d1
TCPD
TCPD
d2
d2
d3
d3
B
B
TDRR
TDRR
d4
d4
C
C
d5
d5
D
D
d6
d6
E
E
d7
d7
F
F
TDRF
TOD
TDRF
TOD
d8
d8
G
G
TCPD
d9
d9
H
H
d10
d10
A
A
d11
d11
B
B
TPD
TPD
d12
d12
C
C
TRDR
TRDR
d13
d3
d4
d5
d6
d7
d8
d9
d13
d3
d4
d5
d6
d7
d8
d9
D
D
d14
d14
E
E
TS81102G0
TROD/TFOD
TROD/TFOD
d15
d15
F
F
TOD
TOD
d16
d16
G
G
TFDR
TFDR
d17
d17
d10
d11
d12
d13
d14
d15
d16
d17
d10
d11
d12
d13
d14
d15
d16
d17
H
H
17