TXC-06880BIOG Transwitch Corporation, TXC-06880BIOG Datasheet - Page 16

• Manufacturer Part Number: TXC-06880BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06880BIOG

• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Envoy-CE2 Device
DATA SHEET
TXC-06880
1 6 o f 12 2
2.1.6 Ingress & Egress Buffering Mechanism
2.1.7 System Packet Interface Level 3 (SPI-3)
Two buffering mechanisms are provided: Store and Forward and Streaming. In Store and
Forward mode, a complete frame is stored in the Ingress and Egress buffers, before it is
transmitted across the SPI-3 and Ethernet interfaces, respectively. In Streaming mode, a
programmable number of bytes are stored in the Ingress and Egress buffers, before the
frame is transmitted across the SPI-3 and Ethernet interfaces, respectively. Hence for low
latency applications, streaming mode provides a solution to transport large frames with
smaller buffer space. The Ingress and Egress buffers can be programmed separately.
The SPI-3 interface operates using an 8, 16, or 32 bit wide pin configurable data bus
(TDAT(31-0) and RDAT(31-0)). The minimum clock (TFCLK and RFCLK) rate is 50 MHz and
the maximum clock rate is 125 MHz. The device can be pin configured to operate as a Link
(Master) or a PHY (Slave) layer device. Multi-PHY (MPHY) and Single-PHY (SPHY) modes
of operation are supported (programmable). Packet level transfer mode is supported in Multi-
PHY mode only and Byte level transfer mode is supported in both Single-PHY and Multi-PHY
modes. On the output interface, chunking is supported where a configured number of bytes
(chunk) are transferred by a port from the PHY device to the Link device. Programmable
packet available thresholds are provided on the input interface. The SPI-3 interface is divided
into the SPI-3 input and the SPI-3 output.
The SPI-3 interface assigns an 8 bit port address with an address range of 0 to 255. The
Envoy-CE2 allows programming of an offset base address for the SPI-3 port address
assignment. The base address is a 3-bit programmable value and is assigned to the most
significant 3 bits of the 8 bit SPI-3 address. Individual SPI-3 port addresses are calculated by
adding the (base address x 32) to the logical Ethernet port number. For example, the SPI-3
address of port 11 with a base address of 3 will give a SPI-3 port address of (11 + (3x32))
=107.
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Functional Description
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PRELIMINARY TXC-06880-MB, Ed. 4
February 2005