TXC-06880BIOG Transwitch Corporation, TXC-06880BIOG Datasheet - Page 95

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TXC-06880BIOG

Manufacturer Part Number
TXC-06880BIOG
Description
Manufacturer
Transwitch Corporation
Datasheet

Specifications of TXC-06880BIOG

Operating Supply Voltage (typ)
1.8/3.3V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TXC-06880BIOG
Manufacturer:
SAMWHA
Quantity:
34 000
2794
2798
27AC RW
27B0
27BC RW
PRELIMINARY TXC-06880-MB, Ed. 4
February 2005
(hex)
Addr
RW
RO
RW
RO
RO
RW
RO
Mode
12-0
31-13
12-0
31-13
15-0
31-16
15-0
31-16
31-0
range
Bit
value after
1FFF
0
1FFF
0
FFFF
0
FFFF
0
FFFFFFFF Ingress FIFO Full Interrupt Mask Per Port: FIFO full interrupt mask for
Default
reset
- Memory Maps and Bit Descriptions -
Flow Control High Threshold CMAC B: This register sets the high
threshold in multiples of 8 bytes, for Ports 8 to 15 (serviced by
Configurable MAC B), for generation of PAUSE frames or asserting raise
carrier. In the event one of the Ethernet port’s ingress FIFO (serviced by
Configurable MAC B) reaches this threshold, a Pause frame will be sent
or raise carrier will be asserted from that port.
Note: Automatic pause frame generation needs to be enabled.
Reserved
Flow Control Low Threshold CMAC B: This register sets the low
threshold in multiples of 8 bytes, for Ports 8 to 15 (serviced by
Configurable MAC B), to stop generation of PAUSE frames or de-
asserting raise carrier. In the event one of the Ethernet port’s ingress
FIFO (serviced by Configurable MAC B) reaches this threshold, when in
the pause frame generation state, further generation of Pause frames
will halt or raise carrier will be de-asserted from that port.
Note: Automatic pause frame generation needs to be enabled. Pause
frame generation state is reached once the Pause high threshold is
crossed.
Reserved
Pause Frame Regeneration Timer CMAC A: This register sets the
Pause frame regeneration time in Pause Quanta (1 Pause Quanta = 512
bit times) for ports 0 to 7, (serviced by Configurable MAC A). The Pause
Frame Regeneration time sets the time between consecutive Pause
frames from an ethernet port, while the port is in the Pause Generation
state. Note: Pause frame generation state is reached once the Pause
high threshold is crossed and the Pause low threshold is not reached.
Reserved
Pause Frame Regeneration Timer CMAC B: This register sets the
Pause frame regeneration time in Pause Quanta (1 Pause Quanta = 512
bit times) for ports 8 to 15, (serviced by Configurable MAC B). The Pause
Frame Regeneration time sets the time between consecutive Pause
frames from an ethernet port, while the port is in the Pause Generation
state. Note: Pause frame generation state is reached once the Pause
high threshold is crossed and the Pause low threshold is not reached.
Reserved
the 16 Ingress FIFOs (one per port). When 0, disables the mask and an
interrupt will be generated when the appropriate FIFO becomes full. The
interrupt is cleared by reading the status register Ingress FIFO Full
Status. If this bit is 1, no interrupt will be generated.
Description
Envoy-CE2 Device
DATA SHEET
TXC-06880
95 o f 12 2

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