82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 77

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

from the multiplexed bus. When the data on the multiplexed bus is input
to the link, the position of the data is arranged by setting the timeslot off-
set.
pin and the framing pulse on the MTSFS pin are provided by the system
side. The signaling bits on the MTSIG pin are per-timeslot aligned with
the corresponding data on the MTSD pin.
is clocked by the MTSCK. The active edge of the MTSCK used to sam-
ple the pulse on the MTSFS is determined by the FE bit. The active
edge of the MTSCK used to sample the data on the MTSD and MTSIG
is determined by the DE bit. If the FE bit and the DE bit are not equal,
the pulse on the MTSFS is ahead. The MTSCK can be selected by the
CMS bit to be the same rate as the data rate on the system side (8.192
MHz) or double the data rate (16.384 MHz). If the speed of the MTSCK
is double the data rate, there will be two active edges in one bit duration.
In this case, the EDGE bit determines the active edge to sample the
data on the MTSD and MTSIG pins. The pulse on the MTSFS pin is
always sampled on its first active edge.
Basic frame, CRC Multi-frame and/or Signaling Multi-frame of the first
link. The indications are selected by the FSTYP bit. The active polarity of
the MTSFS is selected by the FSINV bit. If the pulse on the MTSFS pin
is not an integer multiple of 125 µ s, this detection will be indicated by the
TCOFAI bit. If the TCOFAE bit is enabled, an interrupt will be reported by
the INT pin when the TCOFAI bit is ‘1’.
3.18.2.4
modes. The offset is between the framing pulse on the TSFS/MTSFS
pin and the start of the corresponding frame input on the TSD/MTSD
pin. The signaling bits on the TSIG/MTSIG pin are always per-timeslot
aligned with the data on the TSD/MTSD pin.
different operating modes and the configuration of the offset.
from 0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the
timeslot offset can be configured from 0 to 127 timeslots (0 & 127 are
included).
IDT82P2281
In the Transmit Multiplexed mode, the timing signal on the MTSCK
In the Transmit Multiplexed mode, the data on the system interface
In the Transmit Multiplexed mode, the MTSFS can indicate the
Bit offset and timeslot offset are both supported in all the operating
Refer to Chapter 3.18.1.4 Offset for the base line without offset in
In Non-multiplexed mode, the timeslot offset can be configured
Offset
77
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 44: Related Bit / Register In Chapter 3.18
Note:
* ID means Indirect Register in the Transmit Payload Control function block.
(T1/J1 only)
(T1/J1 only)
TSOFF[6:0]
BOFF[2:0]
FBITGAP
MAP[1:0]
TCOFAE
TMODE
TCOFAI
MTSDA
FSTYP
TMUX
FSINV
EDGE
PCCE
G56K
CMS
GAP
Bit
FE
DE
ID * - Channel Control (for T1/J1) /
Backplane Global Configuration
RTSFS Change Indication
Timeslot Control (for E1)
RTSFS Interrupt Control
TBIF Operating Mode
TPLC Control Enable
TBIF Option Register
TBIF TS Offset
TBIF Bit Offset
Register
T1/J1) / 00~1F (for E1)
TPLC ID * - 01~18 (for
Address (Hex)
August 20, 2009
0CC
04C
010
043
042
045
04B
044