82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 16

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

IDT82P2281
Pin Description
RSCK / MRSCK Output / Input
TSFS / MTSFS Output / Input
TSIG / MTSIG
TSD / MTSD
Name
Type
Input
Input
Pin No.
60
55
54
53
RSCK: Receive Side System Clock
In Receive Clock Master mode, the RSCK pin outputs a (gapped) 1.544 MHz (for T1/J1 mode) / 2.048 MHz (for E1
mode) clock used to update the signal on the RSD, RSIG and RSFS pins.
In Receive Clock Slave mode, the RSCK pin inputs a 1.544 MHz (for T1/J1 mode only), 2.048 MHz or 4.096 MHz clock
used to update the signals on the RSD and RSIG pins and sample the signals on the RSFS pin.
MRSCK: Multiplexed Receive Side System Clock
In Receive Multiplexed mode, MRSCK inputs a 8.192 MHz or 16.384 MHz clock used to update the signals on the MRSD
and MRSIG pins and sample the signal on the MRSFS pin.
RSCK/MRSCK is a Schmitt-triggered input/output with pull-up resistor.
TSD: Transmit Side System Data
The data stream from the system side is input on this pin.
In Transmit Non-Multiplexed mode, the TSD pin is sampled on the active edge of TSCK.
MTSD: Multiplexed Transmit Side System Data
In Transmit Multiplexed mode, the MTSD pin is used to input the data stream. Using a byte-interleaved multiplexing
scheme, the MTSD pin inputs the data for the link. The data on the MTSD pin is sampled on the active edge of MTSCK.
TSD/MTSD is a Schmitt-triggered input.
TSIG: Transmit Side System Signaling
The signaling bits are input on this pin. They are located in the lower nibble (b5 ~ b8) and are channel/timeslot-aligned
with the data input on the TSD pin.
In Transmit Non-Multiplexed mode, TSIG is sampled on the active edge of TSCK.
MTSIG: Multiplexed Transmit Side System Signaling
In Transmit Multiplexed mode, the MTSIG pin is used to input the signaling bits. The signaling bits are located in the
lower nibble (b5 ~ b8) and are channel/timeslot-aligned with the data input on the MTSD pin. Using the byte-interleaved
multiplexing scheme, the MTSIG pin inputs the signaling bits for the link. The signaling bits on the MTSIG pin is sampled
on the active edge of MTSCK.
TSIG/MTSIG is a Schmitt-triggered input.
TSFS: Transmit Side System Frame Pulse
In T1/J1 Transmit Clock Master mode, TSFS outputs the pulse to indicate each F-bit or the first F-bit of every SF/ESF/T1
DM/SLC-96 multi-frame.
In T1/J1 Transmit Clock Slave mode, TSFS inputs the pulse to indicate each F-bit or the first F-bit of every SF/ESF/T1
DM/SLC-96 multi-frame.
In E1 Transmit Clock Master mode, TSFS outputs the pulse to indicate the Basic frame, CRC Multi-frame and/or Signal-
ing Multi-frame.
In E1 Transmit Clock Slave mode, TSFS inputs the pulse to indicate the Basic frame, CRC Multi-frame and/or Signaling
Multi-frame.
TSFS is updated/sampled on the active edge of TSCK. The active polarity of TSFS is selected by the FSINV bit (b1, T1/
J1-042H / b1, E1-042H).
MTSFS: Multiplexed Transmit Side System Frame Pulse
In T1/J1 Transmit Multiplexed mode, MTSFS inputs the pulse to indicate each F-bit or the first F-bit of every SF/ESF/T1
DM/SLC-96 multi-frame of the link on the multiplexed data bus.
In E1 Transmit Multiplexed mode, MTSFS inputs the pulse to indicate each Basic frame, CRC Multi-frame and/or Signal-
ing Multi-frame of the link on the multiplexed data bus.
MTSFS is sampled on the active edge of MTSCK. The active polarity of MTSFS is selected by the FSINV bit (b1, T1/J1-
042H / b1, E1-042H).
TSFS/MTSFS is a Schmitt-triggered input/output with pull-up resistor.
16
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Description
August 20, 2009