82V2044EPFG8 IDT, Integrated Device Technology Inc, 82V2044EPFG8 Datasheet - Page 9

• Manufacturer Part Number: 82V2044EPFG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044EPFG8

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

Notes:
1. The footprint ‘n’ (n = 1~4) represents one of the four channels.
2. The name and address of the registers that contain the preceding bit. Only the address of channel 1 register is listed, the rest addresses are represented by '...'. Users can find
these omitted addresses in the Register Description section.
3. TCLKn missing: the state of TCLKn continues to be high level or low level over 70 clock cycles.
QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
2
Table-1 Pin Description
TD1/TDP1
TD2/TDP2
TD3/TDP3
TD4/TDP4
RRING1
RRING2
RRING3
RRING4
TRING1
TRING2
TRING3
TRING4
TCLK1
TCLK2
TCLK3
TCLK4
RTIP1
RTIP2
RTIP3
RTIP4
Name
TTIP1
TTIP2
TTIP3
TTIP4
TDN1
TDN2
TDN3
TDN4
PIN DESCRIPTION
Output
Analog
Analog
Input
Input
Input
Type
TQFP128
104
103
109
108
114
113
119
118
48
58
47
57
53
63
52
62
96
90
80
74
95
89
79
73
97
91
82
75
TTIPn
These pins are the differential line driver outputs and can be set to high impedance state globally or individually. A logic high on
THZ pin turns all these pins into high impedance state. When THZ bit (TCF1, 03H...)
responding channel is set to high impedance state.
In summary, these pins will become high impedance in the following conditions:
•
•
•
•
•
•
RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 1~4
These pins are the differential line receiver inputs.
TDn: Transmit Data for Channel 1~4
In Single Rail Mode, the NRZ data to be transmitted is input on these pins. Data on TDn is sampled into the device on the active
edge of TCLKn. The active edge of TCLKn is selected by the TCLK_SEL bit (TCF0, 02H...). Data is encoded by AMI, HDB3 or
B8ZS line code rules before being transmitted to the line. In this mode, TDNn should be connected to ground.
TDPn/TDNn: Positive/Negative Transmit Data for Channel 1~4
In Dual Rail Mode, the NRZ data to be transmitted is input on these pins. Data on TDPn/TDNn is sampled into the device on
the active edge of TCLKn. The active edge of the TCLKn is selected by the TCLK_SEL bit (TCF0, 02H...) The line code in Dual
Rail Mode is as follows:
TCLKn: Transmit Clock for Channel 1~4
These pins input 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode transmit clock. The transmit data on TDn/TDPn or TDNn
is sampled into the device on the active edge of TCLKn. If TCLKn is missing
an interrupt will be generated.
THZ pin is high: all TTIPn/TRINGn enter high impedance.
THZn bit is set to 1: the corresponding TTIPn/TRINGn become high impedance;
Loss of MCLK: all TTIPn/TRINGn pins become high impedance;
Loss of TCLKn: the corresponding TTIPn/TRINGn become high impedance (exceptions: Remote Loopback; Transmit
internal pattern by MCLK);
Transmitter path power down: the corresponding TTIPn/TRINGn become high impedance;
After software reset; pin reset and power on: all TTIPn/TRINGn enter high impedance.
1
/TRINGn: Transmit Bipolar Tip/Ring for Channel 1~4
TDPn
0
0
1
1
Transmit and Receive Digital Data Interface
Transmit and Receive Line Interface
TDNn
0
1
0
1
Space
Positive Pulse
Negative Pulse
Space
Output Pulse
9
Description
3
and the TCLKn missing interrupt is not masked,
2
is set to ‘1’, the TTIPn/TRINGn in the cor-
TEMPERATURE RANGES
INDUSTRIAL