82V2044EPFG8 IDT, Integrated Device Technology Inc, 82V2044EPFG8 Datasheet - Page 10

• Manufacturer Part Number: 82V2044EPFG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044EPFG8

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
RD1/RDP1
RD2/RDP2
RD3/RDP3
RD4/RDP4
CV1/RDN1
CV2/RDN2
CV3/RDN3
CV4/RDN4
MCLKS
RCLK1
RCLK2
RCLK3
RCLK4
MCLK
Name
LOS1
LOS2
LOS3
LOS4
P/S
Output
Output
Output
Input
Input
Input
Type
TQFP128
128
93
87
77
71
92
86
76
70
94
88
78
72
10
40
1
2
3
8
RDn: Receive Data for Channel 1~4
In Single Rail Mode, the NRZ receive data is output on these pins. Data is decoded according to AMI, HDB3 or B8ZS line code
rules. The active level on RDn pin is selected by the RD_INV bit (RCF0, 07H...).
CVn: Code Violation for Channel 1~4
In Single Rail Mode, the BPV/CV errors in received data streams will be reported by driving pin CVn to high level for a full clock
cycle. The B8ZS/HDB3 line code violation can be indicated when the B8ZS/HDB3 decoder is enabled. When AMI decoder is
selected, the bipolar violation can be indicated.
RDPn/RDNn: Positive/Negative Receive Data for Channel 1~4
In Dual Rail Mode with Clock & Data Recovery (CDR), these pins output the NRZ data with the recovered clock. An active level
on RDPn indicates the receipt of a positive pulse on RTIPn/RRINGn while an active level on RDNn indicates the receipt of a neg-
ative pulse on RTIPn/RRINGn. The active level on RDPn/RDNn is selected by the RD_INV bit (RCF0, 07H...). When CDR is
disabled, these pins directly output the raw RZ sliced data. The output data on RDn and RDPn/RDNn is updated on the active
edge of RCLKn.
RCLKn: Receive Clock for Channel 1~4
These pins output 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS conditions, if AISE bit
(MAINT0, 0AH...) is ‘1’, RCLKn is derived from MCLK.
In clock recovery mode, these pins provide the clock recovered from the signal received on RTIPn/RRINGn. The receive data
(RDn in Single Rail Mode or RDPn/RDNn in Dual Rail Mode) is updated on the active edge of RCLKn. The active edge is
selected by the RCLK_SEL bit (RCF0, 07H...).
If clock recovery is bypassed, RCLKn is the exclusive OR(XOR) output of the Dual Rail sliced data RDPn and RDNn. This signal
can be used in the applications with external clock recovery circuitry.
MCLK: Master Clock
MCLK is an independent, free-running reference clock. It is a single reference for all operation modes and provides selectable
1.544 MHz or 37.056 MHz for T1/J1 operating mode, while 2.048 MHz or 49.152 MHz for E1 operating mode.
The reference clock is used to generate several internal reference signals:
•
•
•
•
•
•
The loss of MCLK will turn all the four TTIP/TRING into high impedance status.
MCLKS: Master Clock Select
If 2.048 MHz (E1) or 1.544 MHz (T1/J1) is selected as the MCLK, this pin should be connected to ground; and if the 49.152 MHz
(E1) or 37.056 MHz (T1/J1) is selected as the MCLK, this pin should be pulled high.
LOSn: Loss of Signal Output for Channel 1~4
These pins are used to indicate the loss of received signals. When LOSn pin becomes high, it indicates the loss of received sig-
nals in channel n. The LOSn pin will become low automatically when valid received signal is detected again. The criteria of loss
of signal are described in
P/S: Parallel or Serial Control Interface Select
Level on this pin determines which control mode is selected to control the device as follows:
The serial microcontroller interface consists of CS, SCLK, SDI, SDO and SCLKE pins. Parallel microcontroller interface consists
of CS, A[7:0], D[7:0], DS/RD and R/W/WR pins. The device supports non-multiplexed parallel interface as follows:
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLKn signal during a loss of signal condition.
Reference clock during Transmit All Ones (TAO) and all zeros condition. When sending PRBS/QRSS or Inband Loopback
code, either MCLK or TCLKn can be selected as the reference clock.
Reference clock for ATAO and AIS.
High
Low
P/S
P/S, INT/MOT
10
11
3.5 LOS AND AIS
Parallel Microcontroller Interface
Serial Microcontroller Interface
Control Interface
Control Interface
Microcontroller Interface
10
Motorola non-multiplexed
Intel non-multiplexed
DETECTION.
Description
TEMPERATURE RANGES
INDUSTRIAL