COM20020I3V-DZD-TR Standard Microsystems (SMSC), COM20020I3V-DZD-TR Datasheet - Page 33

• Manufacturer Part Number: COM20020I3V-DZD-TR
• Manufacturer: Standard Microsystems (SMSC)

Specifications of COM20020I3V-DZD-TR

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Compliant

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V
3,2,1 Clock Prescaler Bits
BIT
7
6
5
4
0
Pulse1 Mode
Four NACKS
Reserved
Receive All
3,2,1
Slow
Select
BIT NAME
Arbitration
P1MODE
FOUR
NACKS
RCVALL
CKP3,2,1
SLOWARB
SYMBOL
Table 11 - Setup 1 Register
DATASHEET
This bit determines the type of PULSE1 output driver used
in Backplane Mode. When high, a push/pull output is used.
When low, an open drain output is used. The default is
open drain.
This bit, when set, will cause the EXNACK bit in the
Diagnostic Status Register to set after four NACKs to Free
Buffer Enquiry are detected by the COM20020I. This bit,
when reset, will set the EXNACK bit after 128 NACKs to
Free Buffer Enquiry. The default is 128.
Do not set.
This bit, when set, allows the COM20020I to receive all
valid data packets on the network, regardless of their
destination ID. This mode can be used to implement a
network monitor with the transmitter on- or off-line. Note
that ACKs are only sent for packets received with a
destination ID equal to the COM20020I's programmed node
ID. This feature can be used to put the COM20020I in a
'listen-only' mode, where the transmitter is disabled and the
COM20020I is not passing tokens. Defaults low.
These bits are used to determine the data rate of the
COM20020I. The following table is for a 20 MHz crystal:
(Clock Multiplier is bypassed)
NOTE: The lowest data rate achievable by the COM20020I
is 156.25Kbs. Defaults to 000 or 2.5Mbs.
Multiplier output clock speed greater than 20 MHz, CKP3,
CKP2 and CKP1 must all be zero.
This bit, when set, will divide the arbitration clock by 2.
Memory cycle times will increase when slow arbitration is
selected.
NOTE: For clock multiplier output clock speeds greater
than 40 MHz, SLOWARB must be set. Defaults to low.
CKP3
0
0
0
0
1
Page 33
CKP2
0
0
1
1
0
CKP1
0
1
0
1
0
DESCRIPTION
DIVISOR
128
16
32
64
8
156.25Kbs
312.5Kbs
1.25Mbs
SPEED
625Kbs
2.5Mbs
For Clock
Revision 12-06-06