COM20020I3V-DZD-TR Standard Microsystems (SMSC), COM20020I3V-DZD-TR Datasheet - Page 24

• Manufacturer Part Number: COM20020I3V-DZD-TR
• Manufacturer: Standard Microsystems (SMSC)

Specifications of COM20020I3V-DZD-TR

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Compliant

7.0 FUNCTIONAL DESCRIPTION
7.1 Microsequencer
The COM20020I contains an internal microsequencer which performs all of the control operations necessary to carry
out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program counter, two instruction
registers, an instruction decoder, a no-op generator, jump logic, and reconfiguration logic.
The COM20020I derives a 10 MHz and a 5 MHz clock from the output clock of the Clock Multiplier. These clocks
provide the rate at which the instructions are executed within the COM20020I. The 10 MHz clock is the rate at which
the program counter operates, while the 5 MHz clock is the rate at which the instructions are executed. The
microprogram is stored in the ROM and the instructions are fetched and then placed into the instruction registers.
One register holds the opcode, while the other holds the immediate data. Once the instruction is fetched, it is
decoded by the internal instruction decoder, at which point the COM20020I proceeds to execute the instruction.
When a no-op instruction is encountered, the microsequencer enters a timed loop and the program counter is
temporarily stopped until the loop is complete. When a jump instruction is encountered, the program counter is
loaded with the jump address from the ROM. The COM20020I contains an internal reconfiguration timer which
interrupts the microsequencer if it has timed out. At this point the program counter is cleared and the MYRECON bit
of the Diagnostic Status Register is set.
Note*:
Revision 12-06-06
REGISTER
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
SUB ADR
URATION
CONFIG-
NODE ID
STATUS
STATUS
SETUP1
NEXT ID
SETUP2
TENTID
DIAG.
DATA
(R/W) This bit can be Written or Read. For more information see Appendix B.
MY-RECON
RBUS-TMG
P1 MODE
RD-DATA
NXT ID7
RESET
(R/W)*
RI/TRI
MSB
TID7
NID7
D7
A7
DUPID
AUTO-
CCHE
FOUR
NAKS
NID6
TID6
X/RI
NXT
INC
ID6
A6
D6
N
X
0
Table 2 - Read Register Summary
TXEN
DATASHEET
RCV-
NID5
X/TA
TID5
CKU
ACT
NXT
ID5
D5
A5
P1
X
X
0
TOKEN
CKUP0
RCV-
NID4
POR
TID4
NXT
ET1
ALL
ID4
A4
D4
X
0
24
READ
(R/W)*
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
TEST
CKP3
EXC-
NID3
TID3
NAK
NXT
ET2
ID3
D3
EF
A3
X
RECON
TENTID
PLANE
BACK-
SYNC
CKP2
SUB-
NID2
TID2
NXT
AD2
A10
NO-
ID2
A2
D2
NEXT
CKP1
RCN-
SUB-
SUB-
NEW
NID1
TMA
TID1
NXT
TM1
AD1
AD1
ID1
A9
A1
D1
ID
SLOW-
RCM-
SUB-
SUB-
NID0
TID0
LSB
ARB
NXT
TM2
TTA
AD0
AD0
TA/
ID0
A8
A0
D0
SMSC COM20020I 3.3V
X
ADDR
07-0
07-1
07-2
07-3
07-4
00
01
02
03
04
05
06