COM20020I3V-DZD-TR Standard Microsystems (SMSC), COM20020I3V-DZD-TR Datasheet - Page 31

• Manufacturer Part Number: COM20020I3V-DZD-TR
• Manufacturer: Standard Microsystems (SMSC)

Specifications of COM20020I3V-DZD-TR

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Compliant

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20020I 3.3V
2,1,0
BIT
BIT
5-3
2-0
7-0
BIT
BIT
7-3
7
6
7
Read Data
Auto Increment
(Reserved)
Address 10-8
Address 7-0
Reserved
Sub Address 2,1,0
Reset
BIT NAME
BIT NAME
BIT NAME
BIT NAME
RDDATA
AUTOINC
A10-A8
A7-A0
SUBAD
2,1,0
RESET
SYMBOL
SYMBOL
Table 7 - Address Pointer High Register
Table 8 - Address Pointer Low Register
SYMBOL
SYMBOL
Table 10 - Configuration Register
Table 9 - Sub Address Register
DATASHEET
These bits are undefined.
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD2
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by
writing the Configuration Register.
A software reset of the COM20020I is executed by writing a
logic "1" to this bit.
microcontroller interface mode, nor does it affect the
Configuration Register. The only registers that the software
reset affect are the Status Register, the Next ID Register, and
the Diagnostic Status Register. This bit must be brought
back to logic "0" to release the reset.
This bit tells the COM20020I whether the following access
will be a read or write. A logic "1" prepares the device for a
read, a logic "0" prepares it for a write.
This bit controls whether the address pointer will increment
automatically.
increment of the pointer after each access, while a logic "0"
disables this function.
Access Memory section for further detail.
These bits are undefined.
These bits hold the upper three address bits which provide
addresses to RAM.
These bits hold the lower 8 address bits which provide the
addresses to RAM.
0
0
0
0
1
1
1
1
Page 31
SUBAD1 SUBAD0
0
0
1
1
0
0
1
1
A logic "1" on this bit allows automatic
DESCRIPTION
DESCRIPTION
A software reset does not reset the
DESCRIPTION
DESCRIPTION
0 Tentative ID \ (Same
1 Node ID
0 Setup 1
1 Next ID
0 Setup 2
1 Reserved
0 Reserved
1 Reserved
Please refer to the Sequential
Register
/ Register)
/ Config
\ as in
Revision 12-06-06