COM20020I3V-DZD-TR Standard Microsystems (SMSC), COM20020I3V-DZD-TR Datasheet
COM20020I3V-DZD-TR
Specifications of COM20020I3V-DZD-TR
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COM20020I3V-DZD-TR Summary of contents
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Product Features New Features: - Data Rates Mbps - Programmable Reconfiguration Times 28 Pin PLCC and 48 Pin TQFP Packages; Lead-free RoHS Compliant Packages also available Ideal for Industrial/Factory/Building Automation and Transportation Applications Deterministic, (ANSI 878.1), Token ...
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... COM20020I3VLJP for 28 pin PLCC package COM20020I3V-DZD for 28 pin PLCC package lead-free RoHS compliant package COM20020I3V-HD for 48 pin TQFP package COM20020I3V-HT for 48 pin TQFP lead-free RoHS compliant package 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © 2006 SMSC or its subsidiaries. All rights reserved. ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM 2.0 GENERAL DESCRIPTION..............................................................................................................................5 3.0 PIN CONFIGURATIONS .................................................................................................................................6 4.0 DESCRIPTION OF PIN FUNCTIONS FOR TQFP ..........................................................................................8 5.0 PROTOCOL DESCRIPTION .........................................................................................................................11 5 ..................................................................................................................................11 ETWORK ROTOCOL 5 ...............................................................................................................................................11 ...
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Figure 14 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE.................................................51 Figure 15 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE .........................................52 Figure 16 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE .........................................53 Figure 17 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM 2.0 General Description SMSC's COM20020I is a member of the family of Embedded ARCNET Controllers from Standard Microsystems Corporation. The device is a general purpose communications controller for networking ...
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PIN CONFIGURATIONS 24 VDD 1 A0/nMUX nRD/nDS 22 A2/ALE 3 nWR/DIR 21 AD0 4 nCS 20 AD1 5 nINTR 19 AD2 6 nRESET nTXEN RXIN 16 nPULSE2 D5 9 ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM AD0 1 AD1 2 N/C 3 AD2 4 N/C 5 VSS VDD VSS SMSC COM20020I 3.3V COM20020I 48 ...
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DESCRIPTION OF PIN FUNCTIONS FOR TQFP PIN NO NAME SYMBOL 44, 45, Address A0/nMUX 0 A2/ALE Data 0-7 AD0-AD2, D3- 10, 12, 13 47, 48, N/C N 14-17 37 nWrite/ ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM PIN NO NAME SYMBOL 24 nPulse 1 nPULSE1 25 nPulse 2 nPULSE2 28 Receive In RXIN 29 nTransmit nTXEN Enable 21 Crystal XTAL1 Oscillator 22 XTAL2 8, 20, Power ...
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Reconfigure Timer has Timed Out Y Start Reconfiguration Timer (420 mS TA? Transmit NAK Transmit ACK Broadcast Send Packet Y Was Packet Broadcast Activity Set TA for 37.4 us ACK? ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM 5.0 PROTOCOL DESCRIPTION 5.1 Network Protocol Communication on the network is based on a token passing protocol. Establishment of the network configuration and management of the network protocol are ...
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The EF bit in the SETUP2 register must be set when the data rate is over 5 Mbps. 5.3 Network Reconfiguration A significant advantage of the COM20020I is its ability to adapt to changes on the network. Whenever a new ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Idle Time The Idle Time is associated with a NETWORK RECONFIGURATION. Figure 1 illustrates that during a NETWORK RECONFIGURATION one node will continually transmit INVITATIONS TO TRANSMIT until it ...
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Two CRC (Cyclic Redundancy Check) characters. The CRC polynomial used is: X Acknowledgements An Acknowledgement is used to acknowledge reception of a packet affirmative response to FREE BUFFER ENQUIRIES and is sent by the following sequence: An ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM 6.0 SYSTEM DESCRIPTION 6.1 Microcontroller Interface The top halves of Figure 2 and Figure 3 illustrate typical COM20020I interfaces to the microcontrollers. The interfaces consist of a 8-bit data ...
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XTAL1 XTAL2 AD0- ALE A15 RESET nRD nWR nINT1 8051 RXIN TXEN nPULSE nPULSE GND BACKPLANE FIGURE A FIGURE 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE Revision 12-06-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM XTAL1 XTAL2 D0- nRES nIOS R/nW nIRQ1 6801 RXIN nTXEN nPULSE1 nPULSE2 GND FIGURE 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE SMSC COM20020I ...
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High Speed CPU Bus Timing Support High speed CPU bus support was added to the COM20020I. The reasoning behind this is as follows: With the Host interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM In the MOTOROLA CPU mode (DIR, nDS mode), the same modifications apply. RBUSTMG BIT 0 1 6.2 Transmission Media Interface The bottom halves of Figure 2 and Figure 3 ...
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RT LTC1480 or Equiv. COM2002 FIGURE 5 - COM20020I NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS 20MHZ CLOCK (FOR REF. ONLY) 100ns nPULSE1 nPULSE2 200ns DIPULSE RXIN FIGURE 6 - DIPULSE WAVEFORM FOR DATA OF 1-1-0 Revision 12-06-06 5Mbps ARCNET (ANSI 878.1) ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM In typical applications, the serial backplane is terminated at both ends and a bias is provided by the external pull-up resistor. The RXIN signal is directly connected to the ...
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ADDRESS DECODING CIRCUITRY AD0-AD2, D3-D7 STATUS/ nINTR COMMAND REGISTER RESET nRESET LOGIC nRD/nDS nWR/DIR BUS ARBITRATION nCS CIRCUITRY Revision 12-06-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM RAM MICRO- SEQUENCER AND WORKING REGISTERS ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM CABLE TYPE RG-62 Belden #86262 RG-59/U Belden #89108 RG-11/U Belden #89108 IBM Type 1* Belden #89688 IBM Type 3* Telephone Twisted Pair Belden #1155A COMCODE 26 AWG Twisted Pair ...
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FUNCTIONAL DESCRIPTION 7.1 Microsequencer The COM20020I contains an internal microsequencer which performs all of the control operations necessary to carry out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program counter, two ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM ADDR MSB 00 RI/TR1 RD- AUTO- 0 DATA INC (R/W ...
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It minimizes the need for operator interaction with the network. The node determines the existence of other nodes by placing a Node ID value in ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Sub-Address Register The sub-address register is new to the COM20020I, previously a reserved register. Bits 2, 1 and 0 are used to select one of the registers assigned to ...
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BIT BIT NAME SYMBOL 7 Receiver RI Inhibited 6,5 (Reserved) 4 Power On Reset POR 3 Test TEST 2 Reconfiguration RECON 1 Transmitter TMA Message Acknowledged 0 Transmitter TA Available Revision 12-06-06 5Mbps ARCNET (ANSI 878.1) Controller with 2K x ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM BIT BIT NAME SYMBOL 7 My MY- Reconfiguration RECON 6 Duplicate ID DUPID 5 Receive RCVACT Activity 4 Token Seen TOKEN 3 Excessive NAK EXCNAK 2 Tentative ID TENTID ...
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DATA COMMAND 0000 0000 Clear Transmit Interrupt 0000 0001 Disable Transmitter 0000 0010 Disable Receiver b0fn n100 Enable Receive to Page fnn 00fn n011 Enable Transmit from Page fnn 0000 c101 Define Configuration 000r p110 Clear Flags 0000 1000 Clear ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM BIT BIT NAME 7 Read Data 6 Auto Increment 5-3 (Reserved) 2-0 Address 10-8 BIT BIT NAME 7-0 Address 7-0 BIT BIT NAME 7-3 Reserved 2,1,0 Sub Address 2,1,0 ...
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BIT BIT NAME 6 Command Chaining Enable 5 Transmit Enable 4,3 Extended Timeout 1,2 2 Backplane 1,0 Sub Address 1,0 Revision 12-06-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM SYMBOL DESCRIPTION CCHEN This bit, if high, ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM BIT BIT NAME 7 Pulse1 Mode 6 Four NACKS 5 Reserved 4 Receive All 3,2,1 Clock Prescaler Bits 3,2,1 0 Slow Arbitration Select SMSC COM20020I 3.3V Table 11 - ...
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BIT BIT NAME 7 Read Bus Timing Select 6 Reserved 5,4 Clock Multiplier 3 Enhanced Functions 2 No Synchronous Revision 12-06-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM Table 12 - Setup 2 Register SYMBOL DESCRIPTION ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM BIT BIT NAME 1,0 Reconfiguration Timer 1, 0 D0-D7 I/O Address 02H High FIGURE 8 – SEQUENTIAL ACCESS OPERATION 7.3 Internal Ram The integration of the ...
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Sequential Access Memory The internal RAM is accessed via a pointer-based scheme. Rather than interfering with system memory, the internal RAM is indirectly accessed through the Address High and Low Pointer Registers. The data is channeled to and from the ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM If the device is configured to handle both long and short packets (see "Define Configuration" command), then receive pages should always be 512 bytes long because the user never ...
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SHORT PACKET FORMAT ADDRESS 0 1 COUNT = 256-N 2 NOT USED DATA BYTE 1 COUNT DATA BYTE 2 DATA BYTE N-1 255 DATA BYTE N NOT USED 511 N = DATA PACKET LENGTH SID = SOURCE ID DID = ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM The first possibility free buffer is available at the destination node, in which case it responds with an ACKnowledgement. At this point, the COM20020I fetches the ...
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MSB TRI RI TRI FIGURE 10 - COMMAND CHAINING STATUS REGISTER QUEUE 7.4 Command Chaining The Command Chaining operation allows consecutive transmissions and receptions to occur without host microcontroller intervention. Through the use of a dual two-level FIFO, commands to ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM This information will remain in the Status Register until the "Clear Transmit Interrupt" command is issued. Note that the interrupt will remain active until the command is issued, and ...
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Address Pointer Registers, the Configuration Register, or the Setup1 Register. A hardware reset occurs when a low signal is asserted ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM The Receive Activity (RCVACT) bit of the Diagnostic Status Register will be set to a logic "1" whenever activity (logic "1") is detected on the RXIN pin. The Token ...
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The crystal must have an accuracy of 0.010% or better when the internal clock multiplier is turned on. The oscillation frequency must be 20MHz when the internal clock multiplier is turned on. The XTAL2 side of the crystal may be ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM 8.0 OPERATIONAL DESCRIPTION 8.1 Maximum Guaranteed Ratings* Operating Temperature Range........................................................................................................................-40 Storage Temperature Range.........................................................................................................................-55 Lead Temperature (soldering, 10 seconds) ................................................................................................................+325 Positive Voltage on any pin, with respect to ground ...............................................................................................V ...
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PARAMETER Low Output Voltage 2 (D0-D7) High Output Voltage 2 (D0-D7) Low Output Voltage 3 (nINTR) High Output Voltage 3 (nINTR) Low Output Voltage 4 (nPULSE1 in Open-Drain Mode) Dynamic V Supply DD Current Input Pull-up Current (nPULSE1 in Open-Drain ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM AC Measurements are taken at the following points: Inputs: t 2.4V 1.4V 50% 0.4V t 2.4V 1.4V 50% 0.4V Inputs are driven at 2.4V for logic "1" and 0.4 ...
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TIMING DIAGRAMS AD0-AD2, D3-D7 nCS t11 ALE nDS DIR t1 Address Setup to ALE Low t2 Address Hold from ALE Low t3 nCS Setup to ALE Low t4 nCS Hold from ALE Low t5 ALE Low to nDS Low ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM AD0-AD2, D3-D7 nCS ALE nRD nWR t1 Address Setup to ALE Low t2 Address Hold from ALE Low t3 nCS Setup to ALE Low t4 nCS Hold from ALE ...
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AD0-AD2, D3-D7 t1 nCS t11 ALE nDS DIR t1 Address Setup to ALE Low t2 Address Hold from ALE Low nCS Setup to ALE Low t3 nCS Hold from ALE Low t4 t5 ALE Low to nDS Low Valid Data ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM AD0-AD2, VALID D3-D7 t1 nCS t3 t9 ALE nWR nRD t1 Address Setup to ALE Low t2 Address Hold from ALE Low nCS Setup to ALE Low t3 t4 ...
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A0-A2 nCS nRD nWR D0-D7 t1 Address Setup to nRD Active Address Hold from nRD Inactive t2 nCS Setup to nRD Active t3 nCS Hold from nRD Inactive t4 Cycle Time (nRD Low to Next Time Low) t5 nRD Low ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM A0-A2 nCS nRD nWR D0-D7 Address Setup to nRD Active t1 Address Hold from nRD Inactive t2 nCS Setup to nRD Active t3 nCS Hold from nRD Inactive t4 ...
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A0-A2 nCS DIR nDS D0-D7 t1 Address Setup to nDS Active t2 Address Hold from nDS Inactive t3 nCS Setup to nDS Active t4 nCS Hold from nDS Inactive t5 DIR Setup to nDS Active t6 Cycle Time (nDS Low ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM A0-A2 nCS DIR nDS D0-D7 t1 Address Setup to nDS Active t2 Address Hold from nDS Inactive t3 nCS Setup to nDS Active t4 nCS Hold from nDS Inactive ...
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A0-A2 nCS Note 3 nRD t10 nWR D0-D7 Parameter t1 Address Setup to nWR Active t2 Address Hold from nWR Inactive t3 nCS Setup to WR Active t4 nCS Hold from nWR Inactive t5 Cycle Time (nWR t6 Valid Data ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM A0-A2 nCS DIR nDS D0-D7 Parameter t1 Address Setup to nDS Active t2 Address Hold from nDS Inactive t3 nCS Setup to nDS Active t4 nCS Hold from nDS ...
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RXIN Parameter t1 nPULSE1, nPULSE2 Pulse Width t2 nPULSE1, nPULSE2 Period t3 nPULSE1, nPULSE2 Overlap t4 nTXEN Low to nPULSE1 Low t5 Beginning of Last Bit Time to nTXEN High t6 RXIN Active Pulse ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM nRESET nINTR Parameter t1 nRESET Pulse Width*** t2 nINTR High to Next nINTR Low Note period of external XTAL oscillation frequency. XTL Note**: T is period of ...
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PACKAGE OUTLINES OTES dim ensions are in inches ircle indicating pin 1 can appear on a top surface as show n on the draw ing or right above ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM FIGURE PIN TQFP PACKAGE OUTLINE MIN NOMINAL 0.05 A2 1.35 D 8.80 D/2 4.40 D1 6.90 E 8.80 E/2 4.40 E1 6.90 H ...
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APPENDIX A This appendix describes the function of the NOSYNC and EF bits. NOSYNC Bit The NOSYNC bit controls whether or not the RAM initialization sequence requires the line to be idle by enabling or disabling the SYNC command ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Never change the CKP3-1 when the data rate is over 5 Mbps. They must all be zero. C) Shorten The Write Interval Time To The Command Register The COM20020I ...
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The EF bit also controls the resolution of the following issues from the COM20020I Rev Network MAP Generation Tentative ID is used for generating the Network MAP, but it sometimes detects a non-existent node. Every time the Tentative-ID ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM 12.0 APPENDIX B 12.1 Software Identification of the COM20020I Rev B, Rev C and Rev D In order to properly write software to work with the COM20020I Rev B, ...