IDT77V126L200TFI IDT, Integrated Device Technology Inc, IDT77V126L200TFI Datasheet - Page 2

• Manufacturer Part Number: IDT77V126L200TFI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V126L200TFI

• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

77V126L200 Overview
data rate ATM network communications as defined by ATM Forum docu-
ment af-phy-040.000 and ITU-T I.432.5. The physical layer is divided
into a Physical Media Dependent sub layer (PMD) and Transmission
Convergence (TC) sub layer. The PMD sub layer includes the functions
for the transmitter, receiver and clock recovery for operation across 100
meters of category 3 and 5 unshielded twisted pair (UTP) cable. This is
referred to as the Line Side Interface. The TC sub layer defines the line
coding, scrambling, data framing and synchronization.
(such as a switch core or SAR) through an 8-bit Utopia Level 1 interface.
register compatibility with it, but it also has additional register features.
This is an 8-bit muxed address and data bus, controlled by a conven-
tional asynchronous read/write handshake.
marker, and provide LED indication of receive and transmit status.
Auto-Synchronization and Good Signal
Indication
that allow it to achieve 4b/5b symbol framing on any valid data stream.
This is an improvement on earlier products which could frame only on
the escape symbol, which occurs only in start-of-cell or 8kHz (X8) timing
marker symbol pairs.
the 77V126L200 receive section to achieve symbol framing and properly
indicate receive signal status, even in the absence of ATM cells or 8kHz
(X8) timing markers in the receive data stream. A state machine moni-
tors the received symbols and asserts the “Good Signal” status bit when
a valid signal is being received. “Good Signal” is deasserted and the
receive FIFO is disabled when the signal is lost. This is sometimes
referred to as Loss of Signal (LOS).
Operation at Speeds Greater Than 25 Mbps
77V126L200 is also specified to operate at 51.2 and 204.8 Mbps.
Except for the higher bit rates, all other aspects of operation are identical
to the 25.6 Mbps mode.
OSC input pin. OSC is 32 MHz for the 25.6 Mbps line rate, and 64 MHz
for the 51.2 and 204.8 Mbps line rate.
Mbps operation have a higher bandwidth than magnetics optimized for
25.6 Mbps. For 204.8Mbps data rate applications, ST6200T magnetics
from Pulse Engineering can be used. These magnetics have been
tested to work over 10 meters of UTP 5 cable at 204.8Mbps. Table 1
shows some of the different data rates the PHY can operate at using a
IDT77V126L200
The 77V126L200 is a physical layer interface chip for up to 200Mbps
On the cell side, the 77V126L200 connects to an ATM layer device
The 77V126L200 is based on the 77105 and maintains significant
Access to these status and control registers is through the utility bus.
Additional pins permit insertion and extraction of an 8kHz timing
The 77V126L200 features a new receiver synchronization algorithm
ATM25 transceivers always transmit valid 4b/5b symbols, allowing
In addition to operation at the standard rate of 25.6 Mbps, the
The rate is determined by the frequency of the clock applied to the
See Figure 16 for recommended line magnetics. Magnetics for 51.2
2 of 30
32MHz or 64MHz oscillator. Note that any oscillator frequency between
32MHz and 64MHz can be used. For example, if a 48MHz oscillator is
used and the multiplier is set to 4x, the data rate would be 153.6Mbps.
Clock (OSC)
Reference
32 MHz
64 MHz
Table 1 200 Speed Grade Option
Clock Multiplier
(Enhanced Control 2
Control Bits
Registers)
00 (1x)
01 (2x)
10 (4x)
00 (1x)
01 (2x)
10 (4x)
Line Bit
(MHz)
Rate
128
128
256
December 2004
32
64
64
(Mbps)
Data
Rate
102.4
102.4
204.8
25.6
51.2
51.2